How to power FPGA in IPTV system?

At present, more and more household appliances are shifting from low-speed dial-up Internet access to broadband Internet access or Internet Protocol Television (IPTV), especially IPTV is expected to achieve rapid development in China. In comparison, the infrastructure cost of IPTV is quite low, because this method does not require copper cables, but uses DSL or broadband links and set-top boxes to stream programs to household appliances.
Today's programmable gate arrays (FPGAs) have proven to be ideal choices for such platforms because they provide the flexibility to quickly change market requirements. The power requirements of FPGAs are usually very complex, because FPGAs have up to three power requirements. In order to achieve reliable system performance, these requirements must be sequenced.
Core voltage
The core voltage rail is usually set to VCCINT to power FPGA logic. The required current ranges from hundreds of milliamps to tens of amperes, depending on the clock frequency and the number of gates used. Because the load is highly capacitive, the core voltage and current requirements may be very high at the beginning. The FPGA core has strict requirements for transient response. The core power supply voltage must increase slowly and is often required to rise to a stable voltage within a fixed length of time. For example, Xilinx's Virtex-4 must allow the VCCINT power supply to power up between 0.2ms and 50ms.
I/O voltage
I/O voltage (VCCIO) usually requires a voltage rail of 3.3V, 2.5V, 1.8V or 1.5V. The I/O standard can be independently set by the I/O module in the FPGA, so an FPGA may have more than one I/O voltage. The I/O current requirement depends on the number of I/Os used and the clock speed. Generally, I/O current requirements are low, ranging from a few hundred mA to 3A.
Auxiliary voltage
The auxiliary voltage (VCCAUX) requires the power supply to have a high power supply rejection ratio (PSRR) because the power supply is directly connected to the digital clock management (DCM). If power supply noise is allowed to couple to the DCM, it may affect the performance of the system.
Although the I/O and auxiliary voltages do not need to be powered up in a particular order, FPGA manufacturers often specify or track the power-on sequence of the core and I/O. The consequences of not specifying the power-on sequence or tracking the power-on sequence are often irreparable damage to the devices in the system. FPGAs, PLDs, DSPs, and microprocessors usually place diodes between the core and the I/O power supply as ESD protection components. If the power supply violates the tracking requirements and exceeds the forward bias of the protection diode, then the device may be damaged.
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solution
To illustrate the complexity of FPGA power supply requirements, take the requirement of powering on VCCINT in a fixed time period as an example. In order to ensure the power-on time between 2ms and 50ms controlled by the upper and lower limits, the circuit shown in Figure 1 should be implemented.

Figure 1: MIC37302 and discrete circuits ensure controlled slope and timing
The power-on sequence or power-on sequence tracking of the core and I/O power supplies increases the complexity and cost of the power management circuit. To overcome this problem, design engineers need a device that meets all these needs without adding external components. An example of this product is Micrel's MIC68200 LDO, which is suitable for various on-board power supplies. It integrates functions such as rising speed control, power-up sequencing and tracking into a 3×3mm MLF package.
Multiple MIC68200s can be cascaded in two modes: in the tracking mode, the output of the master device drives the RC pin of the slave device so that the slave device can track the master regulator during turn-on and turn-off; in the sequential power-up mode, the master The POR of the device drives the enable (EN) end of the slave device so that it is turned on after the master device is turned on and turned off before (or after) the master device is turned off. In addition to tracking capabilities, the voltage ramp control (RC) pin can also accurately program the ramp voltage of the core voltage rail through a capacitor.
The tracking and sorting circuits are shown in Figure 2 and Figure 3, respectively. It can be seen from the figure that the solution is a simple and requires few discrete components.

Figure 2: Tracking circuit, the slope of the core voltage is set by the capacitor on the RC pin

Figure 3: Sequencing circuit, the POR of the master regulator enables the slave regulator, and the POR delay is set by the low capacitance

Summary of this article
In short, the advantages of using FPGA as an encoding and decoding platform in IPTV video broadcasting are obvious. However, powering the FPGA may be a challenge, and the use of dedicated power management devices designed according to power requirements, such as the MIC68200, will greatly shorten the time to market for new systems.

 

 

 

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