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When it comes to the structure of FPGAs, people usually think like this: The basic structure of FPGAs is composed of a large number of relatively small programmable logic blocks "islands" embedded in the "sea" of programmable interconnection. At first glance, it feels a bit clouded and misty, but after careful consideration, the expression of literary and artistic fan is indeed the case:
At present, more than 90% of FPGAs on the market come from the two giants xilinx and altera, and the implementation technologies of these two FPGAs are based on SRAM programmable technology. The internal structure of the FPGA is basically the same, so this article only uses xilinx 7 series FPGAs. Introduction.
CLB is the basic logic unit of xilinx FPGA. Each CLB contains two slices, and each slice consists of 4 6-input LUTs (look-up tables) and 8 D flip-flops. The two slices in the same CLB are not directly connected by lines, and belong to two different columns. Each column has an independent fast carry chain resource. Let's take a look at the structure of the basic logic unit CLB. As shown in Figure 1, there are four CLBs listed:
Figure 1: CLB structure
The basic structure inside the FPGA is composed of thousands of such CLBs. There are a large number of signal interconnections between CLBs and CLBs, which serve as channels for data flow. The "island" mentioned at the beginning is the CLB, and the "sea" is the signal interconnection line. Of course, this is only the most basic FPGA structure. The actual FPGA internal "sea" has to be embedded with other "Pearls" in order to work normally, such as clock modules, memory, network modules, transceiver modules, etc., the more the number of "Pearls" More, the richer the FPGA functions, and of course the more expensive it is.
So, you may have doubts, how can CLB realize complex digital logic functions? Don't forget that the above explained that 1 CLB contains 2 slices, and each slice is composed of 4 6-input LUTs, 8 D flip-flops, and multiple MUXs. To put it simply, LUT is a lookup table, which can realize combinatorial logic functions in digital logic, such as C=A+B; D flip-flops realize sequential logic functions; MUX enhances the flexibility of internal signal circulation in Slice.
That is to say, combinatorial logic and sequential logic can be flexibly implemented within 1 Slice, so what about 1 CLB (equal to 2 Slices)? How about thousands of CLBs? So FPGA can realize very complicated digital operation.
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