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FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the deficiencies of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.
1. How FPGA works
FPGA adopts the concept of logic cell array LCA (Logic Cell Array), which includes three parts: Configurable Logic Block (CLB), IOB (Input Output Block), and Interconnect. A field programmable gate array (FPGA) is a programmable device. Compared with traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices), FPGA has a different structure. FPGA uses a small lookup table (16×1RAM) to implement combinational logic, and each lookup table is connected to a D flip-flop The flip-flops then drive other logic circuits or drive I/O to form a basic logic unit module that can realize both combinational logic functions and sequential logic functions. These modules are connected to each other or connected by metal wires. To the I/O module. FPGA logic is realized by loading programming data into the internal static storage unit. The value stored in the memory unit determines the logic function of the logic unit and the connection between modules or between modules and I/O, and finally determines The function that FPGA can realize, FPGA allows unlimited programming.
2. Basic Features
1) Using FPGA to design ASIC circuit (application-specific integrated circuit), users do not need to produce chips, and can get a suitable chip.
2) FPGA can be used as a sample chip for other fully customized or semi-customized ASIC circuits.
3) There are abundant flip-flops and I/O pins inside the FPGA.
4) FPGA is one of the devices with the shortest design cycle, the lowest development cost, and the lowest risk in ASIC circuits.
5) FPGA uses high-speed CMOS technology, low power consumption, and compatible with CMOS and TTL levels.
It can be said that FPGA chips are one of the best choices for small-batch systems to improve system integration and reliability.
FPGA is set by the program stored in the on-chip RAM to set its working state, therefore, it is necessary to program the on-chip RAM when working. Users can adopt different programming methods according to different configuration modes.
When power is on, the FPGA chip reads the data in EPROM into the on-chip programming RAM. After the configuration is completed, the FPGA enters the working state. After a power failure, the FPGA is restored to a blank, and the internal logic relationship disappears. Therefore, the FPGA can be used repeatedly. The programming of FPGA does not need a dedicated FPGA programmer, only general EPROM and PROM programmers. When you need to modify the FPGA function, you only need to change a piece of EPROM. In this way, the same piece of FPGA, different programming data, can produce different circuit functions. Therefore, the use of FPGA is very flexible.
3. FPGA configuration mode
FPGA has a variety of configuration modes: the parallel master mode is one FPGA plus one EPROM; the master-slave mode can support one PROM to program multiple FPGAs; the serial mode can use serial PROM to program the FPGA; the peripheral mode can use the FPGA as a micro The peripherals of the processor are programmed by the microprocessor. How to achieve fast timing closure, reduce power consumption and cost, optimize clock management and reduce the complexity of FPGA and PCB parallel design, etc., have always been key issues that system design engineers using FPGAs need to consider. Nowadays, as FPGAs develop toward higher density, larger capacity, lower power consumption, and more IP integration, system design engineers have to face the unprecedented performance and performance of FPGAs while benefiting from these excellent performances. New design challenges brought about by ability level. For example, the Virtex-5 series recently launched by leading FPGA manufacturer Xilinx uses a 65nm process and can provide up to 330,000 logic cells, 1,200 I/Os and a large number of hard IP blocks. Large capacity and density make complex wiring more unpredictable, which brings more serious timing closure problems. In addition, the greater number of logic functions, DSPs, embedded processing and interface modules integrated for different applications also make clock management and voltage distribution issues more difficult. Fortunately, FPGA vendors and EDA tool suppliers are working together to solve the unique design challenges of 65nm FPGAs. Not long ago, Synplicity and Xilinx announced the establishment of an ultra-large-capacity timing closure joint working group aimed at helping system design engineers to apply 65nm FPGA devices in a faster and more efficient manner. The synthesis tool Blast FPGA launched by design software supplier Magma can help establish an optimized layout and speed up timing closure. Recently, FPGA configuration methods have been diversified!
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