The audio delay can be used for live broadcasts of radio stations. It delays the audio signal for a period of time before broadcasting, so as to avoid the host’s slip of the tongue or some unhealthy comments from the audience in the audience hotline from spreading through the broadcasting media, thereby achieving the safe broadcasting of live programs. As a broadcast-level equipment, audio delayers have high requirements for performance indicators such as dynamic range, distortion, signal-to-noise ratio, and frequency response, so digital technology is generally used. Using the computer's built-in full-duplex sound card hard disk, the audio signal blinking can be realized by software, but it is inconvenient to use and operate, the reliability is poor, and the performance and price are relatively low. The broadcast-grade digital audio delayer based on high-precision Σ-ΔADC and DSP chip proposed in this paper has the characteristics of high performance index, simple operation and complete functions. The design scheme has been commercialized.
1 System structure
1.1 System configuration
The delayer hardware is a master-slave structure, as shown in Figure 1, which is mainly composed of a single-sleeper M transmitter 8HC05C8, a DSP chip MTS320C32, and an audio codec CS4224. M68HC05C8 is used as the host of the whole system to complete the control function of the system. As the core of the system, TMS320C32 completes the audio signal delay function. CS4224 and audio input and output conditioning circuit work together to complete the A/D and D/A conversion of audio signals.
The audio delay can be used for live broadcasts of radio stations. It delays the audio signal for a period of time before broadcasting, so as to avoid the host’s slip of the tongue or some unhealthy comments from the audience in the audience hotline from spreading through the broadcasting media, thereby achieving the safe broadcasting of live programs. As a broadcast-level equipment, audio delayers have high requirements for performance indicators such as dynamic range, distortion, signal-to-noise ratio, and frequency response, so digital technology is generally used. Using the computer's built-in full-duplex sound card hard disk, the audio signal blinking can be realized by software, but it is inconvenient to use and operate, the reliability is poor, and the performance and price are relatively low. The broadcast-grade digital audio delayer based on high-precision Σ-ΔADC and DSP chip proposed in this paper has the characteristics of high performance index, simple operation and complete functions. The design scheme has been commercialized.
1 System structure
1.1 System configuration
The delayer hardware is a master-slave structure, as shown in Figure 1, which is mainly composed of a single-sleeper M transmitter 8HC05C8, a DSP chip MTS320C32, and an audio codec CS4224. M68HC05C8 is used as the host of the whole system to complete the control function of the system. As the core of the system, TMS320C32 completes the audio signal delay function. CS4224 and audio input and output conditioning circuit work together to complete the A/D and D/A conversion of audio signals.
CS4224 is a high-performance 24-bit audio codec. It uses Σ-Δ technology to provide full-duplex stereo digital/analog and analog/digital conversion, with a dynamic range of 105dB, harmonic distortion and operation of -97dB, and a sampling frequency of 32kHz , 44.1kHz and 48kHz are optional. The chip adopts differential input and output, with on-chip anti-aliasing filter, output smoothing filter and digital de-emphasis filter circuit, with analog volume control, supporting master or slave working mode.
TMS320C32 is a low-cost, high-performance floating-point DSP chip, very suitable for voice digital signal processing. It supports 24-bit address bus and 32-bit data bus, and can address the large-capacity memory required by the delayer. It also has a serial interface to facilitate the CS4224 interface with serial audio data input and output.
M68HC05C8 realizes man-machine interface, manages keyboard display and delayer remote control interface, and controls the operation of CS4224 and TMS320C32.
1.2 Memory interface
TMS320C32 has an enhanced external memory interface, the program memory can be 16-bit and 32-bit wide, and the data memory can be 8/16/32-bit wide. TMS320C32 uses two sets of strobe signals STRB1 and STRB0, which have different addressing ranges. Each group of strobe signals consists of four pins, which are used as chip selects and additional address lines. The characteristics of the pins are determined by the bus control register corresponding to each group of strobe signals. By setting certain fields of the bus control register, you can specify the data type and the width of the external memory.
The delay uses two sets of memories with different widths. SRAM stores audio data. Set the memory width to 32 bits and the data type to 32 bits. Since the audio codec CS4224 is 24 bits, it actually uses 24 bits and consists of three 8-bit SRAMs, each with STRB0_B0~2 chip selection. FLASH chip 28F512 stores user audio signal processing program, the memory width is 8 bits, and ATRB1_B0 chip selection is used.
The memory interface mainly considers memory speed to determine how many wait states need to be inserted. Because the TMS320C32 clock frequency is 40MHz, and the access speed of FLASH memory is 150ns, and the access speed of SRAM is 70ns, a wait state must be inserted. TMS320C32 has an internal programmable software wait state generator, select the working mode of the wait state generator through the SWW domain of the STRBx control register, and write the number of machine cycles to wait in the WTCNT domain. Since the program memory and data storage are respectively strobed by STRB1 and STRB0, the required number of machine cycles can be set according to their respective access speeds.
TMS320C32 has a program guide function. When the hardware is reset, the MCBL/MP pin is high, then it works in microcomputer mode, executes the on-chip boot program, and loads the user program in the FLASH memory into the internal high-speed RAM to run. The boot mode can be determined by pin INT0～3, the external memory load address is selected as Boot3 area according to the connection mode of the memory, and the handshake signal is not used. The front end of the FLASH memory is the program header, including the necessary information for TMS320C32 when booting, such as the width of the external memory, the contents of the bus control register after the boot, the length of each data block, the width of the target memory, and the data type.
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