"Based on expert interviews, technical evaluation and industry analysis, the editorial, reporter and analyst team of aspencore, the world's largest electronic industry media group, compiled the top 10 technology trends in the semiconductor industry in 2020:
1. 5g "large scale"
2. Calculate "Marginalization"
3. Wafer manufacturing "isomerization"
4. Chip "specialization"
5. The computing architecture is "open"
6. EDA moves towards "cloud"
7. MEMS / sensor "fusion"
8. GaN / SiC new material "substitution"
9. Memory device market "recovery"
10. High performance "simulation"
1、 5g "large-scale" commerce will drive the development of 5g mobile phones, base stations, VR / AR equipment, as well as emerging applications such as industry 4.0, automatic driving and medical treatment
5g is relative to 4G network, just as China's high-speed railway is relative to traditional ordinary railway, high speed, low delay and large capacity are the remarkable characteristics of 5g network. 3GPP defines three technologies and application scenarios of 5g, namely: enhanced mobile broadband (embB), mainly for 3D / ultra-high definition video, VR / AR and other applications; Mass machine communication (mmtc), mainly for Internet of things applications such as smart wearable, smart home, smart city, Internet of vehicles and industrial Internet of things; High reliability and low time delay (urllc), mainly for high reliability key applications such as automatic driving, industrial automation and mobile medical treatment. The increasing maturity of 5g technology and the large-scale commercial deployment of 5g network will drive the development and popularization of AI, big data and cloud computing in emerging application fields such as video games, VR / AR, aiot, automatic driving, smart city, industry 4.0 and medical imaging.
In 2020, 5g will enter the large-scale commercial stage, which will first drive the rapid development, technological innovation and mass shipment of chips and electronic components for 5g mobile phones, wireless base stations and communication network systems, including modem and baseband chips for 5g mobile phones, application processors, GPU and AI accelerators, RF devices and filters, image sensors / cameras, antennas and other components; As the 5g network operates at a higher frequency (sub-6ghz), the shortcomings of fast signal attenuation and short transmission distance of 5g base stations force operators to deploy and install at least three times the number of 4G base stations to achieve full coverage, which will drive the demand for baseband digital signal processing devices, RF devices, power amplifier devices, antennas and power management devices (the power consumption of 5g base stations is 2-3 times that of 4G).
The high-speed and low delay characteristics of 5g network can just solve the pain point of "poor user experience" of VR / ar. the electronic engineering album predicts that this will drive a new round of VR / Ar / MR upsurge. Facebook will invest a lot of money in developing headset devices and even acquire chip companies to develop its own integrated hardware platform; AR applications will be deployed for patrol inspection operations in power and manufacturing industries, which can better provide remote information interaction and support with 5g network; More than 30% of the exhibition scenes will provide VR / AR equipment, software, content and services; Universities and training institutions will also adopt VR / AR for course training.
5g technology can also network separately for manufacturing enterprises, boost the development of industry 4.0, industrial Internet of things and industrial big data, and ensure the security of enterprise data. In addition, 5g will also drive the accelerated landing of Internet of vehicles and ADAS / autopilot, and provide high-speed, stable and safe data transmission for emerging applications such as telemedicine and medical imaging.
2、 The trend of "Marginalization" of computing gives more AI and computing power to edge devices, which not only provides more opportunities for SoC design companies, but also puts forward higher PPA requirements
The dispersion and fragmentation of Internet of things application scenarios have brought great pressure on the transmission network bandwidth and cloud computing capacity, forcing IOT terminal devices to have the ability to process data locally. This demand has driven the rise of edge computing, improved the performance of microprocessors at the core of edge devices, and correspondingly enhanced AI processing capacity. Edge computing can collect and analyze data on IOT devices, make rapid reasoning (or decision), and then transfer only a small amount of useful data to the cloud. In this way, the delay time, bandwidth consumption and cost will be reduced, and decisions can be made quickly according to data analysis. Even if the system is offline, edge computing can continue to run, process data immediately and determine which data should be transferred to the cloud for further analysis.
As the heart of IOT edge or terminal equipment, system level chip (SOC) should not only have better performance, but also have as low power consumption and occupied area as possible, that is, it needs to achieve the best PPA. The traditional general-purpose MCU / MPU / CPU has been difficult to meet the requirements of different application scenarios and PPA. The innovation of technology and business model in the field of edge computing can release the potential of AI and computing power. In addition, different application scenarios have different requirements for software and AI algorithms. Although it is technically feasible to add AI reasoning function on the edge side, customized chips are needed to realize processors with AI enhanced performance. Small and medium-sized enterprises and start-ups focus more on application software and AI algorithms, while large and medium-sized enterprises pay more attention to the ecological construction of edge computing. For example, Huawei participates in or leads the formulation of industry standard protocols and software and hardware development environment.
In terms of Internet of things communication protocol, global telecom operators are pushing NB IOT, especially in the Chinese market. Lora, ZigBee, Bluetooth and other communication protocols also have their own development ways and main application fields, but the coexistence of multiple standards and protocols will be the current situation of IOT market in the future. SoC design engineers and microprocessor developers must consider the compatibility and support of multiple protocols.
3、 Wafer manufacturing "isomerization" integration encapsulates dies of different process nodes together through 2.5d/3d stacking technology, chiplet or a new IP for chip design and manufacturing in the post Moore era
High performance CPU, smartphone AP, GPU and FPGA have always been "early adopters" of the most advanced process nodes below 14nm. TSMC's 7Nm process is the most advanced mass production technology at present. It is expected that 5nm process will replace it as the most high-end process in 2020. In this craft competition, which is more expensive than building aircraft carriers, only TSMC, Samsung and Intel are competing in the world. Are 3nm, 2nm and 1nm nodes next? Even if there is enough money to invest in R & D, the physical limit of Moore's law has seen an end. Where is the future of semiconductor manufacturing?
2.5D and 3D stacked packaging technology has become a "heterogeneous integration" solution generally recognized by wafer foundry, IDM and packaging and testing manufacturers, because it can integrate bare chips of different process nodes and meet the requirements of various devices in high, medium and low-end markets. Silicon via (TSV) is one of the earliest stacking technologies. At present, the packaging technology competition from TSV to wafer level stacking is mainly concentrated between "TSV" and "TSV less". For high-performance devices, the most popular 2.5D and 3D integration technologies are 3D stacked storage TSV and heterogeneous stacked TSV intermediary layer. TSMC, UMC, lattice core and other wafer foundry manufacturers are leading the technological development in this regard. The foveros technology developed by IDM manufacturer Intel is based on "active" TSV intermediary layer and 3D SoC technology. Samsung, SK Hynix and micron, the "big three" of storage, dominate the competition and development of 3D stacked storage.
These bare chips that are "Heterogeneous Integrated" in a chip through stacked packaging have different functions and different process nodes. However, if unified interface standards are used for data communication and transmission, chip design, manufacturing and packaging can be greatly simplified. Therefore, the concept of chip came into being and began to be accepted by the semiconductor industry. DARPA of the United States has specially set up a chips (Universal heterogeneous integration and IP reuse strategy) project to promote the research and development of chiplet. Intel has also opened its AIB (advanced interface bus) interface to support a wide range of chiplet ecosystem. TSMC cooperates with arm to develop a 7Nm chiplet system using chip on wafer on substrate (cowos) packaging technology, which is composed of two Chiplets. Each chiplet contains four arm cortex A72 processors and an on-chip interconnect bus. With the development of wafer manufacturing and packaging heterogeneous integration, chiplet may evolve from concept to a general technology and bare chip form, and even become a new IP in the post molar era.
4、 Chip "specialization" opens the application-oriented customized chip design idea, and AI chip will become a massive data processing accelerator for data center, terminal equipment and automatic driving
Google's TPU is a concrete embodiment of the "domain specific architecture" advocated by John Hennessy and David Patterson, 2017 Turing Award winners. It is an example of AI chip development led by software, algorithms and applications according to the special needs of Google's cloud platform. The switch from general-purpose CPU, GPU and FPGA to special SOC and AI accelerator chips is to meet the massive data processing challenges of various emerging applications, including high-performance computing in the data center, extensive and scattered application scenarios of the Internet of things, and real-time processing and decision-making required by autopilot and industry 4.0.
Not only Internet giants such as Google, Amazon and Alibaba and hypescaler cloud computing service providers began to develop their own special chips, Tesla is also developing its own "full self driving (FSD)" chips. These non-standard, non-commercial chips are customized and developed to meet the specific application needs of these companies, because they can't buy the desired chips from traditional chip manufacturers. Even Xilinx, a traditional FPGA manufacturer, has begun to transform from a chip to a platform company. Its focus will turn to high-performance data centers and specific application fields with strict and flexible requirements for computing. The products provided will also expand from FPGA chips to software, AI computing power and platform services.
VC's investment in the semiconductor industry has increased rapidly since 2017, and AI chip start-ups are most favored by VC. However, in the next 2-3 years, these AI unicorns with huge financing will look for application scenarios everywhere with chips. Horizon, with a financing amount of up to $600 million, began to plough deeply in the fields of automatic driving and aiot, while graphcore, which advocates the concept of computational graphs (graphs represent knowledge models and applications, and all machine learning models are expressed in the form of graphs), has found a place for its IPU in its investors Dell, EMC and Microsoft. There are many other AI chip startups looking for their own "sweet spot".
5、 The "openness" of computing architecture stimulates open source hardware innovation, and the rapid development of risc-v ecology impacts the global chip design community and arm ecology
From the perspective of computer instruction set architecture (ISA), x86 and arm are historical choices, but next will be the "golden decade of computer architecture" declared by Professor Patterson of Berkeley. Moore's law, which has dominated the development of integrated circuits for many years, is coming to an end, and von Neumann architecture, which has supported the development of computers for many years, has begun to highlight its limitations. General purpose CPU, GPU, FPGA and ASIC all have their own expertise and limitations, and heterogeneous computing has increased the complexity of computing on this basis, To meet these challenges posed by emerging applications, we must fundamentally carry out architecture innovation.
Risc-v has set off an upsurge of open source hardware and open chip design, which has been supported by many large and medium-sized enterprises, scientific research institutions and start-ups around the world. The ecology and community growing around risc-v are also developing rapidly. From basic risc-v ISA and core IP to development environment and software tools, as well as venture capital are promoting the further expansion of risc-v ecology. In the context of the Sino US science and technology cold war, the development of China's chip design industry urgently needs an independent and open computing architecture. Rsic-v just caters to this demand, which seems to have been proved by the rapid development in China in just two years.
If PC / server makes x86 and smartphone makes arm, then the next aiot will support risc-v to become the mainstream computing architecture and even the mainstream chip design and development trend. Arm has felt the pressure and began to make changes, such as opening customized instructions and more open collaboration with industry partners in the field of IOT and automatic driving. While the arm camp was robbed by risc-v, arm also began to enter the PC server market. We will see more ARM processors from Amazon, Huawei and Qualcomm infiltrate into traditional x86 territories such as PC computers and servers.
6、 EDA moves towards "cloud" and supports AI, extending the design scope from chip to system, so as to improve the consistency of the whole system design
TSMC cooperated with cadence, Synopsys, Amazon AWS and Microsoft azure to establish a cloud platform based virtual design environment (OIP VDE), and successfully designed the first 64 bit multi-core risc-v CPU in the cloud for sifive streaming. Arm also cooperates with EDA manufacturers to provide its ecological partners with the latest cloud design platform of ARM processor, which can now support TMSC 7Nm process nodes. EDA to the cloud is the general trend, and will fundamentally change the chip design process and mode.
Significant progress has been made in applying machine learning to chip design. From signal integrity and power integrity to dividing the product portfolio into system analysis, chip layout and trusted platform design, AI can set dozens of options in EDA tools to help accelerate the automation process. In the first stage of AI application, cadence uses data analysis to create a machine learning model for parasitic parameter acquisition, so as to accelerate long-term calculation. The next stage of introducing AI into EDA tools will aim at layout and routing tools, so that AI can learn from human designers and recommend optimization schemes that can accelerate running time. There are many opportunities in EDA industry to use machine learning technology to realize automatic decision-making and optimize the overall design process.
Mentor's acquisition by Siemens also marks the beginning of EDA's expansion from chip design to system design. Internet giants and system manufacturers purchase EDA tools and design their own chips and systems, which also accelerates this expansion trend. With the gradual implementation of digital twin and virtual physical system (CPS) from the concept, traditional EDA tools have gradually become an organic part of the whole product life cycle management of intelligent manufacturing. The design scope covers electronic, electrical, mechanical and thermal characteristics. At the same time, signal and power integrity, functional and information security, verification and integration, and manufacturability (DFM) are moving from the system end (rightmost end) to the left, making increasingly complex systems
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