The MAX120 is a new product, which has recently been newly launched by US Maxim, using a 12-bit analog digital converter for sampled circuitry produced by BICMOS, and sets track / holder (T / H), and precision electrical derived. Its conversion time is 1.6μs, the sampling rate is 500ksps, the internal and external sampling mode is optional, the continuous conversion mode is optional, the input voltage is ± 5V, the limit value is ± 15V, the power consumption is 210MW, the full temperature is slidable, can be lost Convenient with the general microprocessor interface, it is suitable for high-speed data acquisition processing systems to meet high speed, high-precision data processing requirements.
The following is a brief introduction to the main pin and function of the chip.
● MODE is an input. When Mode = VDD, int / busy uses an interrupt signal; when mode = open or mode = DGND, INT / BUSY is used as a busy output;
● Convst is the conversion start input, and the conversion starts during the falling edge of the waveform;
● INT or BUSY output represents the state of the converter;
● CS is a slice selected, which is valid. When it is low, three-state data output is allowed; when CONVST and RD are low, the falling edge of the CS is initiated once.
● RD is the read input, which is valid. When it is low, it allows three-state data to output; when the convst and Rd are low, the falling edge of the RD starts a transition.
Operating mode
MAX120 has 5 working modes.
● Full control mode (Mode 1): Provides maximum control capabilities to control the start and number of operations of the conversion. The full control method is used to insert or cannot insert a microprocessor system (μP) of the waiting state, and can interface with the DSP bus.
● Independent mode (mode 2) and continuous conversion mode (mode 5): is a system for no processor, or for processor-based systems, that is, the ADC and processor in the system are buffered by advanced first out (FIFO) buffer. The device or direct memory access (DMA) is generally not directly connected to the DSP.
● Slow storage mode (Mode 3): Mainly used to enable a system that can be entered into the waiting state during the ADC conversion period, and can be used with the DSP bus interface.
● ROM mode (mode 4): The system used for the processor cannot be entered into the waiting state, and can interface with the DSP.
In these five working modes, the start of the converter is controlled by one of three digital input signals (CONVST, RD or CS). In any way, it is necessary to start the conversion must cause convst to a low level. Once the conversion is entered, it cannot be started again. The read operation is controlled by RD and CS. To read output data, this two digital input signal must be low, and the operating status of the int / busy output converter determines when the last transition time is valid.
In addition, the mode input Mode has the following statements for the output of INT / Busy:
If Mode = VDD, INT / BUSY is an interrupt signal. At this time, INT / BUSY is a low level, and after the conversion data is read, INT / BUSY returns a high level.
If Mode is open or connected to a digitally, INT / BUSY makes Busy output. At this time, INT / BUSY becomes low when the conversion is started, and the conversion is highly valid after D0 to D11.
MAX120 interface instance
General analog signals must be buffered before performing A / D conversion to reduce the impact on the A / D converter. This interface circuit uses the LF353 high-speed integrated op amp composition signal buffer amplifier, as shown.
The analog signal is input by the AIN. CLKIN is an A / D conversion pulse input terminal of the A / D converter, which takes 80 c32 by a single-chip ALE side. Convst is connected to the P1.0 port of the microcontroller, starting A / D conversion at the pulse falling edge. The output of the data is selected from the chip selection CS and RD control; Y0, Y1, Y2 take the output of the decoder connected to the single chip. Y0 and RD Control the data output of the A / D converter, when Y0 is valid, the falling edge of the RD edge output data, the RD rising edge is reversed by the reverse device as the input latch pulse of the latch 74f373, and converts the conversion output The 12-bit data lock is in 2 latches. Y1 and RD are used to control low 8-bit data in the read latch; Y2 and RD are used to control high 4-bit data in the read latch.
Conclude
There are many A / D conversion chips for the data acquisition system, and the application field is also relatively wide, and the MAX120 is a new member of the A / D family, that is, the function of the current product, the speed and accuracy of data acquisition. Large extent, in automatic control systems such as voice, noise and other signal processing systems and dynamic performance requirements, as data acquisition components are ideal.
Editor in charge: GT, read full text
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