"21 special function registers (26 in 52 Series) are discontinuously distributed in the 128 byte SFR storage space, and the address space is 80h-ffh. In this SFR space, there are 128 bit address spaces, and the address is also 80h-ffh, but there are only 83 significant bit addresses, Bit addressing operation can be performed on some bits of 11 special function registers (a skill is introduced here: the address that can be divided by 8 can be bit addressed).
In the 51 single chip microcomputer, there is a CPU for operation and control, four parallel I / O ports, P0, P1, P2 and P3, ROM for storing programs, ram for storing intermediate results, timing / counter, serial I / O port, interrupt system and an internal clock circuit. In the single chip microcomputer, there are some independent storage units used to control these devices, which are called special function register (SFR). There are 21 such special function registers in 51 single chip microcomputer and they are addressable. The list is as follows (the special function registers added by 52 series with * sign):
They are described as follows:
1. ACC --- accumulator, usually represented by A
What is this? It can't be understood from the name. It's a register, not an addition thing. Why give it such a name? Perhaps it is because one of the numbers must be in ACC when the arithmetic unit performs operations. Its name is special and its identity is also special. We will learn instructions later in the second part. We can find that all operation instructions are inseparable from it. It has all zero flag Z, if a = 0, z = 1; If a ≠ 0, z = 0. This flag is often used as a judgment condition for program branching and transfer.
2. B -- one register
When doing multiplication and division, put multipliers or divisors. When not doing multiplication and division, use them as you like.
3. PSW -- program status word.
This is a very important thing. It contains many states of the CPU when it is working. Therefore, we can understand the current state of the CPU and deal with it accordingly. See the following table for its functions:
Let's introduce your uses one by one
Cy: carry flag.
The arithmetic unit in 8051 is an 8-bit arithmetic unit. We know that the 8-bit arithmetic unit can only represent 0-255. If you add, the sum of the two numbers may exceed 255. In this way, the highest bit will be lost, resulting in operation errors. What should we do? Come here at the top. So it's okay. With advance and borrow, cy = 1; No borrowing and borrowing, cy = 0, example: 78h + 97h (01111000 + 10010111)
AC: auxiliary carry / borrow (carry / borrow between high and low nibbles).
Example: 57h + 3ah (01010111 + 00111010)
F0: user flag bit
It is up to the user (Programmer) to decide when to use and when not to use.
RS1, rs0: working register group selection bit
By modifying the status of RS1 and rs0 bits in PSW, you can select any working register area. This feature improves the speed of MCS-51 field protection and field recovery. It is very beneficial to improve the working efficiency of CPU and the speed of responding to interrupt. If four groups of working registers are not needed in a practical application system, the redundant units in this area can be used as a general data buffer.
0V: overflow flag bit
The operation result is understood according to complement operation. Overflow, OV = 1; No overflow, OV = 0. What is overflow? We'll talk about it later.
P: Parity bit
It is used to represent the parity of the number of binary digits "1" in the ALU operation result. If it is an odd number, P = 1, otherwise it is 0. The operation result has an odd number of 1, P = 1; The operation result has an even number of 1, P = 0.
Example: the result of an operation is 78h (01111000). Obviously, the number of 1 is even, so p = 0.
4. Dptr (DPH, DPL) -- data pointer
It can be used to access any unit in the external data memory. If it is not used, it can also be used as a general register. It is up to us to decide how to use it. It is divided into two registers: DPL (low 8 bits) and DPH (high 8 bits). It is used to store 16 bit address value, so as to perform data operation in the range of 64K bytes on off-chip data RAM or program memory by means of indirect addressing or index addressing.
5. P0, P1, P2, P3 ------- input / output port (I / O) register, as we already know, is the register of four parallel input / output ports (I / O). Its contents correspond to the output of the pin.
6. Ie -- interrupt enable register
Bit addressable, address: a8h
EA (ie.7): when EA = 0, all interrupts are prohibited (i.e. no interrupt is generated); When EA = 1, the generation of each interrupt is determined by individual allowable bits - (ie.6): reserved
ET2 (ie.5): timed 2 overflow interrupt allowed (for 8052)
ES (ie.4): serial port interrupt allowed (ES = 1 allowed, ES = 0 prohibited) ET1 (ie.3): timed 1 interrupt allowed
EX1 (ie.2): external interrupt INT1 interrupt allowed
ET0 (ie.1): timer 0 interrupt allowed
Ex0 (ie.0): interrupt permission of external interrupt INT0
7. IP -- interrupt priority control register
Addressable by bit, address bit b8h
-(IP. 7): reserved
-(IP. 6): reserved
PT2 (IP. 5): timing 2 interrupt priority (for 8052)
PS (IP. 4): serial port interrupt priority
PT1 (IP. 3): timing 1 interrupt priority
PX1 (IP. 2): external interrupt INT1 interrupt priority
PT0 (IP. 1): timer 0 interrupt priority
Px0 (IP. 0): interrupt priority of external interrupt INT0
8. Tmod -- timer control register
Non bit addressing, address 89h
Gate: timing operation switch control bit. When gate = 1, INT0 or INT1 pin is high level, and tr0 or Tr1 control bit in TCON is 1, timing / counter 0 or 1 starts to work. If gate = 0, the timer / counter 0 or 1 starts working as long as the tr0 or Tr1 control bit is set to 1.
C / T: selection bit of timer or counter function. C / T = 1 is the counter, and the counting pulse is input through the external pin t0 or T1. When C / T = 0, it is a timer, and the internal system clock provides timing working pulse.
M1, M0: T0, T1 working mode selection bit
9. TCON -- timer control register
Addressable by bit, address bit 88H
TF1: timer T1 overflow flag, which can be queried and cleared by the program. TF1 is also the interrupt request source. When the CPU responds to T1 interrupt, it is cleared by the hardware.
TF0: timer T0 overflow flag, which can be queried and cleared by program. TF0 is also the interrupt request source. When CPU responds to t0 interrupt, it is cleared by hardware.
Tr1: digital control position of T1 permissive meter. When it is 1, T1 counting is allowed.
Tr0: t0 enable count control bit, when it is 1, t0 count is allowed.
IE1: external interrupt 1 request source (INT1, p3.3) flag. IE1 = 1, external interrupt 1 is requesting an interrupt from the CPU. When the CPU responds to the interrupt, the hardware clears "0" IE1 (edge trigger mode).
It1: trigger mode control bit of external interrupt source 1. It1 = 0, external interrupt 1 is programmed as level trigger mode. When INT1 (p3.3) inputs low level, set IE1.
Ie0: external interrupt 0 request source (INT0, p3.2) flag. Ie0 = 1, external interrupt 1 is requesting an interrupt from the CPU. When the CPU responds to the interrupt, the hardware clears "0" ie0 (edge trigger mode).
It0: trigger mode control bit of external interrupt source 0. It0 = 0, external interrupt 1 is programmed as level trigger mode. When INT0 (p3.2) inputs low level, set ie0.
10. Scon --- serial communication control register
It is an addressable special register used for communication control of serial data. The unit address is 98H. Its structure format is as follows:
(1) SM0, SM1: serial port working mode control bit.
SM0, SM1 working mode
00 mode 0-baud rate is determined by oscillator frequency: oscillator frequency / 1201 mode 1-baud rate is determined by overflow rate of timer T1 or T2 and SMOD: 2smod ×( T1 overflow rate) / 3210 mode 2 - baud rate is determined by oscillator frequency and SMOD: 2smod × Oscillator frequency / 6411 mode 3 - baud rate is determined by overflow rate of timer T1 or T2 and SMOD: 2smod ×( T1 overflow rate) / 32 (2) SM2: multi machine communication control bit< Br > multi machine communication works in mode 2 and mode 3, and SM2 bit is mainly used in mode 2 and mode 3. Receiving status: when the serial port works in mode 2 or 3 and SM2 = 1, only when the received 9th bit data (rb8) is 1, the received first 8 bits of data are sent to SBUF, and the setting RI sends an interrupt application, otherwise the received data will be abandoned. When SM2 = 0, no matter whether the bit data is 0 or 1, the data is sent to SBUF and an interrupt application is issued.
When working in mode 0, SM2 must be 0.
(3) Ren: allow to receive bit< Br > Ren is used to control the permission and prohibition of data reception. When Ren = 1, reception is allowed, and when Ren = 0, reception is prohibited.
(4) TB8: send receive data bit 8< Br > in modes 2 and 3, TB8 is the 9th data bit to be sent. This bit is also transmitted in multi machine communication, and it represents the transmitted address or data. TB8 = 0 is the data, and TB8 = 1 is the address.
(5) Rb8: receive data bit 8.
In modes 2 and 3, rb8 stores the received 9th bit data to identify the characteristics of the received data.
(6) Ti: send interrupt flag bit.
Addressable flag bit. In mode 0, after the 8th bit data is transmitted, it is set by the hardware. In other modes, it is set by the hardware before the transmission or stop bit. Therefore, Ti = 1 indicates the end of frame transmission, and Ti can be cleared by the software.
(7) RI: receive interrupt flag bit.
Addressable flag bit. After receiving the 8th bit data, the bit is set by hardware. In other working modes, the bit is set by hardware. RI = 1 indicates that the frame reception is completed.
11. PCON ---- power management register
PCON is mainly a special register set for the power control of CHMOS single chip microcomputer. The unit address is 87h. Its structure format is as follows:
In CHMOS single chip microcomputer, except for SMOD bit, other bits are dummy. SMOD is the baud rate doubling bit of serial port. When SMOD = 1, the baud rate of serial port is doubled. System reset defaults to SMOD = 0.
12. T2con ---- T2 status control register
TF2: T2 overflow interrupt flag. TF2 must be cleared by the user program '0'. When T2 is used as serial baud rate generator, TF2 will not be set to "1".
Exf2: timer T2 external interrupt flag. When exen2 is 1, when t2ex (P1.1) has negative jump, set 1 interrupt flag dxf2, and exf2 must be cleared "0" by the user program.
TCLK: transmission clock selection flag of serial interface. When TCLK = 1, T2 works in baud rate generator mode.
RCLK: receive clock selection flag bit of serial interface. When rCLK = 1, T2 works in baud rate generator mode.
Exen2: external interrupt enable flag of T2.
C / T2: external counter / timer selection bit. When C / T2 = 1, T2 is the external event counter, and the counting pulse comes from T2 (P1.0); When C / T2 = 0, T2 is the timer and the twelve frequency division signal of the oscillation pulse is the counting signal.
TR2: T2 count / timing control bit. When Tr1 is 1, counting is allowed, and when Tr1 is 0, counting is prohibited.
CP / RL2: capture and constant auto reload mode selection bit. When it is 1, it works in capture mode, and when it is 0, T2 works in constant automatic reload mode. When TCLK or rCLK is 1, CP / RL2 is ignored and T2 always works in constant automatic reload mode.
The D0, D2, D4 and D5 bits of t2con mainly control the working mode of T2, and the combination relationship of these bits is summarized below., Read the full text“
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