The following description: 1, ACC --- is an accumulator, usually use a to say this is something, can not be understood from the name, it is a register, instead of making an additional thing, why give it a name? Maybe because one of them will be in the ACC when the operator is calculated. Its name is special, the identity is also special, and later in the middle section we will learn the instructions, you can find that all the computing classes are inseparable from it. Itself with a full zero z, if a = 0 is z = 1; if a ≠ 0 z = 0. This logo is often used as a judgment condition for program branching. 2, b - one register is multiplied by multiplication, division, while doing multiplication, how do you use it? 3, PSW ----- Program status word. This is a very important thing, there is a lot of status when the CPU is working, there we can understand the current state of the CPU and make corresponding processing. If you have functions, please see the following table: Below we will introduce you to the use of the use cy: carry mark. The operator in 8051 is an 8-bit operator. We know that the 8-bit operator can only represent 0-255, if you do addition, the two numbers may exceed 255, so the highest bit will be lost. What should I do if the error is caused? The highest bit will come here. This is fine. Advance, borrow, cy = 1; no borrowing, cy = 0 case: 78h + 97h (01111000 + 10010111) AC: auxiliary, borrow (high half-byte and low half-word downtown, excuse me). Example: 57h + 3ah (01010111 + 00111010) F0: When the user logo is determined by the user (programmer), when is it not used. RS1, RS0: The working register group selection bit can optionally be a working register area by modifying the RS1 and RS0 status in the PSW. This feature increases the speed of MCS-51 on-site protection and live recovery. It is advantageous to improve the efficiency and response interruption of the CPU. If in an actual application system, no four sets of working registers are required, the excess units in this area can be used as a general data buffer. 0V: The result of overflow flag is understood by complement. Overflow, OV = 1; no overflow, OV = 0. What is overflowing our chapters. P: The parity bit is used to indicate the parity of the number of binary digits "1" in the ALU computation result. If odd, P = 1, otherwise 0. The calculation results are odd 1, p = 1; the calculation results have even numbers 1, p = 0. Example: An operation result is 78H (01111000), apparently 1 number is an even number, so P = 0.4, DPTR (DPH, DPL) -------- Data pointer can be used to access external data storage Any unit in the middle, if not, it can also be used as a general register, and we have determined how to use it. Divided into DPL (low 8 bits) and DPH (high 8 bits) two registers. Used to store 16-bit address values to use indirect addressing or address addressing to perform data operations within 64k bytes of the 34k byte range. 5, P0, P1, P2, P3 -------- Enter the Output Port (I / O) Register This we already know that it is a register of four parallel input / output port (I / O). The content inside corresponds to the output of the pin. 6, IE ----- Interrupt Roof register can be bitten, address: A8HEA (IE.7): EA = 0, all interrupts are disabled (ie, no interrupt); EA = 1, each interrupt Generation is determined by individual permission sites - (IE.6): retains ET2 (IE.5): Timed 2 overflow interrupt allows (8052) ES (IE.4): Serial port interrupt allowance (ES = 1 Allow, ES = 0 Prohibit) ET1 (IE.3): Timing 1 Interrupt Allow EX1 (IE.2): Outside Interrupt INT1 Interrupt Allow ET0 (IE.1): Timer 0 Interrupt Allow EX0 (IE.0): External Interrupt INT0 Interrupt allowed 7, IP ----- Interrupt Priority Control Register can be addressed, address bit B8H- (IP.7): Reserved - (IP.6): Keep PT2 (IP.5): Timing 2 Interrupt Priority (8052) PS (IP.4): Serial Oral Interrupt Priority PT1 (IP.3): Timer 1 Interrupt Priority PX1 (IP.2): Outer Interrupt INT1 Interrupt Priority PT0 (IP.1): Timer 0 Interrupt priority PX0 (IP.0): Interrupt of external interrupt INT0 8, TMOD ----- Timer control register is not bitset, address 89HGATE: Timed operation switch control bit, when Gate = 1, INT0 or The INT1 pin is high, and the TR0 or TR1 control bit in TCON is 1, the timing / counter 0 or 1 starts working. If GATE = 0, the TR0 or TR1 control bit is set to 1, and the timing / counter 0 or 1 will begin. C / T: Select Bits of Timers or Counters. C / T = 1 is a counter, and the counting pulse is input by external pin T0 or T1. When C / T = 0 is a timer, the timing working pulse is provided by the internal system clock. M1, M0: T0, T1 Operation Mode Select Bit 9, TCON ------ Timer Control Register can be addressed, address bit 88HTF1: Timer T1 overflow flag, can be queried and cleared by the program, TF1 is also an interrupt request Source, when the CPU response T1 is interrupted by the hardware. TF0: Timer T0 overflow flag can be queried and cleared by the program, and the TF0 is also an interrupt request source that is cleared by the hardware when the CPU responds to T0. TR1: T1 is allowed to the count control bit, and the T1 count is allowed to be 1. TR0: T0 is fully a count control bit, and a T0 count is allowed for 1. IE1: External Interrupt 1 Displays the source (INT1, P3.3) logo. IE1 = 1, the external interrupt 1 is interrupted to the CPU, and when the CPU responds to the "0" IE1 (edge trigger mode). IT1: External Interrupt Source 1 Trigger mode control bit. IT1 = 0, the external interrupt 1 is controlled to level trigger mode, when INT1 (P3.3) is input low, set IE1. IE0: External Interrupt 0 Please show the source (INT0, P3.2) logo. IE0 = 1, the external interrupt 1 is interrupted to the CPU, and when the CPU response occurs, "0" IE0 (edge trigger mode) is cleared by the hardware. IT0: External interrupt source 0 trigger mode control bit. IT0 = 0, the external interrupt 1 is controlled to level trigger mode, when INT0 (P3.2) inputs low level, set IE0.10, SCON ---- Serial Communication Control Register It is a dedicated Registers, communication control for serial data, unit address is 98h, and its structural format is as follows: (1) SM0, SM1: Serial port operation mode control bit. SM0, SM1 Working Method 0-baud rate is determined by the oscillator frequency: oscillator frequency / 1201 mode 1-baud rate is determined by the timer T1 or T2 deficit and SMOD determined: 2SMOD × (T1 overflow rate) / 3210 Method 2-Baud Rate is determined by the oscillator frequency and SMOD: 2SMOD × oscillator frequency / 6411 mode 3-baud rate is determined by the timer T1 or T2 defers: 2SMOD × (T1 overflow rate) / 32 (2) SM2: Multi-machine communication control bit. < BR> Multi-machine communication is to work in a manner 2 and mode 3, and the SM2 bits are mainly used in ways 2 and mode 3. The receiving state, when the serial port is operated in mode 2 or 3, and SM2 = 1, only when the 9th bit data (RB8) is received, the resulting top 8 bit data is sent to SBUF, and the setting The bit ri issued an interrupt request, otherwise the received data will be abandoned. When SM2 = 0, no matter whether the first data is 0 or 1, it is difficult to send SBUF, and issue an interrupt application. When working in mode 0, SM2 must be 0. (3) REN: Allows the reception bit. < REN is used to control the allowable and prohibition of data reception, when Ren = 1, when receiving, ren = 0, prohibiting reception. (4) TB8: Send the received data bit 8. < BR> In Ways 2 and Ways 3, TB8 is the 9th bit data bit to be sent. The same also transmits this bit in the multi-machine communication, and it represents the transmitted address or data, TB8 = 0 is data, TB8 = 1 is the address. (5) RB8: Receive the data bit 8. In the modes 2 and mode 3, RB8 stores the received ninth bit data to identify the received data characteristics. (6) TI: Send an interrupt flag. Addressable marking. At the time of the mode 0, after sending the 8th bit, after the hardware is set, in other ways, the hardware is set by the hardware before sending or stopping the bits, and therefore, Ti = 1 represents the end of the frame transmission, and Ti can be "0" by software. (7) RI: Receive interrupt flag. Addressable marking. After receiving the 8th bit, the bit is set by hardware, and the bit is set by hardware, and Ri = 1 represents the completion of the frame reception. 11. PCON ----- The power management register PCON is mainly a dedicated register set for the power control of the CHMOS type single chip microcomputer. The unit address is 87h, and the structure format is as follows: In the Chmos type single-chip, except for the SMOD, other positions All are dummy, Smod is a serial port baud rate multiplier, when SMOD = 1, the serial port bass is doubled. System reset defaults to SMOD = 0.12, T2CON ----- T2 Status Control Register TF2: T2 overflow interrupt flag. TF2 must be clear "0" by the user program. When T2 is used as a serial baud rate generator, TF2 will not be set "1". EXF2: Timer T2 external interrupt flag. When Exen2 is 1, when the T2EX (P1.1) occurs, it is time to set the interrupt flag DXF2, and EXF2 must be clear "0" by the user program. TCLK: Send Clock Select Sign for Serial Interface. When TCLK = 1, T2 works in the baud rate generator mode. RCLK: The receiving clock selection flag of the serial interface is selected. When RCLK = 1, T2 works in the baud rate generator mode. Exen2: T2 of the external interrupt. C / T2: External Counter / Timer Select Bits. At C / T2 = 1, T2 is an external event counter, and the count pulse is from T2 (P1.0); C / T2 = 0, T2 is a timer, the oscillating pulse is a count signal. TR2: T2 count / timing control bit. Tr1 is 1 when counting, and counts when 0 is 0. CP / RL2: Capture and constant automatic reload mode selection bit. At 1 time, it works in the capture mode, and T2 is 0 when T2 is automatically reloaded. When TCLK or RCLK is 1, CP / RL2 is ignored, and T2 is always working in a constant automatic reloading method. The following is a primary control of T2's working mode for T2CON's D0, D2, D4, and the combination relationship of these digits is summarized below. Read the full article, original text title: [Practical] 51 single-chip register function list
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