555 Timer (TIMER) is named by 3 5k ohm partial voltage resistors inside, is a multi-purpose modulus mixed integrated circuit, which can easily constitute a Schmitt trigger, a single stable trigger and more Harmonic oscillator, and low cost and reliable performance, wide application in various fields.
The schematic diagram shown below:
Among them, the second pin TRIGER is the external low level signal trigger end, and the 5th pin is cont (control) as a voltage control terminal, and the reference voltage of the internal two comparators can be changed by an external voltage. The pin is stringed into a 0.01U capacitor to ground to prevent interference. The 6th THRES (Threshold) is a high level trigger end, and the 7th foot discH (discharge) is a discharge end, which is connected to the collector of the internal discharge triode, and the discharge of the capacitance at the time of timer.
555 Timer The most basic function is timing, substantial is a single steady trigger, that is, the plus signal can generate time-controlled pulse width, the width of this pulse is the timing time we need. . In order to more conveniently describe the principle of 555 timer, we first use the circuit shown below to simulate the single-stable trigger circuit:
The single-stable trigger circuit is a negative pulse trigger, so we set the cycle of 50ms, while the high level width is 49ms, that is, the negative pulse (low) width is 1 ms, the simulation waveform is shown below:
As can be seen from the waveform map, each negative pulse (low) signal (orange), the circuit outputs a pulse (blue) of the fixed width, the output pulse width of this circuit is determined by the resistor R1 and the capacitor C1, about For 1.1R1C1 (ie 1.1 × 1 × 10 = 11 ms), we will measure the details of the actual data, as shown below:
The simulated output pulse width is about 11.0347ms, which is very close to the theoretical value. In order to further analyze the working principle of the circuit, we use four channel oscilloscopes to track the three signal waveforms shown below:
Its waveform is shown below:
As with the previous waveform, only the waveforms of the THR and the DIS pin (connected together), we will enlarge some of them as shown below:
The three 5K resistors within the 555 chip will 5V DC power supply voltage, where 2/3 (about 3.6V) supply comparator CMP1 is supplied to the inverting end of the comparator CMP2. When the inverted end of the comparator CMP1 is grounded, when the circuit is just powered up, since the voltage at both ends of the capacitor C1 cannot be mutated, the voltage ratio of the inverter is low in the same phase end, so the comparator CMP1 outputs a high level h (trigger due to RS triggering The server is a digital logic, so the post-level circuit is distinguished by high level H and the low level L). For comparator CMP2, the default level of the same phase end is high (negative pulse trigger), which is 1.6V higher than the inverse phase end voltage, and therefore, the comparator CMP2 output is also high H.
Since r = h, s = h, the RS trigger is in the state, we assume that the 555 timing chip is in the reset state, at which point the flip-flop is output to high h (or low level, the last result is the same) After an inverter NOT, the circuit is output to a low level L, which is shown in the following figure:
On the other hand, the high level h of the trigger output causes the triode Q1 to beat it, at which time the 7th pin DISCH is pulled low L (corresponding to the capacitor C1 in the discharge state), this pin is simultaneously with the comparator CMP1 The inverted end is the same potential, the maintenance comparator CMP1 is output to h, at which time the circuit is a stable state, and the output is low level attention to the electronic production station dzzzcn, in this loneliness, quietly waiting for the external trigger signal Assembly, I have a bit of starry night, as shown below:
If the external trigger (low level) signal has not arrived, the circuit has kept the output to a low level L, the waveform is shown below:
The emperor did not have a person, and finally waited until the long-standing negative level trigger pulse. The same phase end voltage of the comparator CMP2 is lower than the inverting terminal voltage, and since r = h, s = L, the RS trigger is in Set the low level L, on the one hand, the inverter NOT outputs high level H, on the other hand, the triode Q1 is turned off, at this time, the DC 5V power supply is charged by the resistor R1, and the sixth foot Threshold potential begins to rise. , As shown below:, Read the full article, original title: Graphic Title Analysis Circuit: 555 Single State Trigger Circuit
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