Rockhouse / Enter Output Interface (Chip Selected Address 74LS273)
; Name: Runa
; Autor:
Content: P1.0 ~ P1.7 Received Light Diode L1 ~ L8
CSEG AT 4000H; Define the starting address, why is it 4000h?
; Memory: program memory, data storage uniform address, up to 64K, ROM (16K) on board; RAM
(32K) for users to expand to 48K. User memory start address is 4000H; 8051 original
The interrupt entry address is positioned in the corresponding address after the offset 4000h.
LJMP START
CSEG AT 4100H
Start:
Mov A, # 01H; Let the first light emitting diode light, the reason for the selection # 01 is to add inverter
LOOP:
MOV P1 A; output from P1 port to the light emitting diode
Delay500ms:; delay 0.5 seconds
MOV R7, # 0bh dl1:
MOV R6, # 5ch DL0:
MOV R5, # 7ah DJNZ R5, $ DJNZ R6, DL0 DJNZ R7, DL1
RL A; right left, light down a light emitting diode
Ljmp loop
End
Name: The input output interface (the closing of the read switch is still open); autor:; time: April 12, 2012, 18: 22: 12; Content: P1.0 ~ P1.7 Pickup button K1 ~ K8; 74LS273 The SO0 ~ SO7 receives the optical diode L1 to L8, the slice selective CSU 8 \ picks CS0 (determined by the entry address selected by the program).
Port EQU 0CFA7H; chip select address CS0 CSEG AT 4000H; absolute addressing, the same
LJMP START
CSEG AT 4100H
Start:
MOV P1, # 0ffh
LOOP:
MOV A, P1; read switch state from P1 port
Mov dptr, #port
MOVX @dptr, A; output from 74LS273 to LED
Ljmp loop; circulating END
Chip selection address 74LS172 connection
74LS273 is an eight-bit data / address latch. This example uses a 74LS273 extended I / O output port, and the value lock on the data bus is stored in 74LS 273 by a chip select signal and a write signal, and data is output at the port of 74LS273. When the value on the data bus is canceled, the output end of 74LS273 remains unchanged due to the 74LS273, so that the new data is latched until the new data is latched.
Hardware design
Create a new Design, add the following components (omitted crystal and reset circuit):
Component name in class reference
AT89C51MICROPROCESSOR ICS
8051 Family
Single-chip microcomputer
LED-YellowOptoelectronics
Leds
led
ResResistors
Generic270Ω resistance
74LS273TTL 74LS series
FLIP-FLOP & LATCHES Double Steady Multivatriotic & Block Loskeepers
74LS32TTL 74LS Series
Gates & Inverters Door Circuit & Follower or Door
The output data of the microcontroller is displayed with 8 light-emitting diodes, and the output is low when the LED light is on. The 74LS273 of D0 ~ D7 is an 8-bit data input, and the P0 port of the monard machine, Q0 ~ Q7 is 8-bit data output, and the CLK is the trigger clock input, MR is the data clearance enable end. The address decoding is performed using or don't have the gate 74LS32, and the input of U3: A is separately connected to the P2.7 port and WR port of the monard, and the CLK port ending 74LS273 is output.
As can be seen from the true value table of 74LS273, when MR is low, all Q terminals are 0, otherwise the Q terminal is determined with the D end, so MR should be high. The CLK completes the data latch operation when the rising edge, so the output of U3: A must complete a change in low to high. When the write instruction is valid, the output is low, only P2.7 is low at low levels, in order to implement a low to high level when the write instruction is completed, so after the write is completed, the data is locked by 74LS273. It can be seen that the 74LS273 address should be 0xxx xxxx xxxx xxxx, usually we have 7FFF.
2. Programming
In Keil C51, there are the following memory types:
Code reads the program memory read by MOVC A, @ a + DPTR
Data can directly access internal data storage
Idata Access in MOV @RN Access Internal Data Memory
BDATA can be addressed within the internal memory of bit addressable
XData Access to the external data store accumulated by MOVX @dptr
PDATA access to external data stores accessed by MOVX @RN
In order to define the convenience of use, the macro definition is performed in the ABSACC.H file, such as the address 0x7FFF in this example, is written as Xbyte [0x7FFF].
#include "AT89X51.H"
#include "absacc.h"
#define a74273 xbyte [0x7fff]
Void main (void)
{
A74273 = 0x2b;
While (1);
}
Note: When the write instruction is valid (it should be WR, if it is not effective), the output low is low, only P2.7 is low at the same time, and it can achieve a low to high level when the write instruction is completed. In this way, the data is locked by 74LS273 after the write is completed. It can be seen that the 74LS273 address should be 0xxx xxxx xxxx xxxx, usually we have 7FFF. Read more
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