"1. Introduction
In the design of traditional narrowband wireless receiver, DVGA + anti aliasing filter + ADC link, we default that the ADC is in high resistance state, and ignore the influence of ADC internal resistance when simulating anti aliasing filter. However, with the rapid development of wireless technology, the required signal bandwidth is wider and wider, and the corresponding signal frequency is higher and higher. In this case, the internal resistance of ADC with frequency will not be ignored. In order to obtain better signal in band flatness, the design of ADC front-end matching circuit is introduced, especially for non input buffer ADC. In the application scenario of high load anti aliasing filter, the design of front-end matching circuit is particularly important in UWB application. This paper will take ads58h40 as an example to introduce the design of ADC front-end matching circuit.
2. Non input buffer ADC internal resistance characteristics and its equivalent model
The input internal resistance of the ideal ADC should be in the high resistance state, that is, the influence of the ADC internal resistance does not need to be considered in the design of the front-end anti aliasing filter, but the actual ADC internal resistance is not infinite and will change with the frequency. From the perspective of input internal resistance, ADC can be divided into two categories. One is ADC with input buffer, the input characteristics tend to be ideal ADC, and the internal resistance is often large; The other is the ADC without input buffer. Their internal resistance can not be ignored at high frequency and changes with frequency, but their power consumption is smaller than the former. Figure 1 shows the equivalent internal resistance model of non input buffer ads58h40 analog input. The equivalent impedance network of ADC analog input sample and hold circuit itself changes with the change of frequency; In addition, the existence of the ADC's glitch absorbing circuit RCR circuit improves the SNR and SFDR of the ADC, but also makes the internal resistance of the ADC change more and more with the frequency. The superposition of the two effects makes the equivalent load of ADC capacitive as a whole.
Figure 1 equivalent internal resistance model of ads58h40 analog input
Figure 2 takes ads58h40 as an example to show the curve of internal resistance varying with frequency. A series model, the series equivalent resistance in the series model is in the order of ohm. B parallel model: the parallel equivalent resistance value in the parallel model is in the order of kohm at low frequency (100MHz), but with the continuous increase of input frequency (200MHz), the parallel equivalent resistance value will drop sharply to the hundred ohm level, so that it can not be ignored relative to the ADC end load of anti aliasing filter. Moreover, the equivalent capacitance in both parallel model and series model also makes the load characteristics of the anti aliasing filter ADC deviate from the ideal resistive characteristics and need to be compensated.
Fig. 2 simplified model of internal resistance of ads58h40: a series model, B parallel model; And its related frequency variation curve
3. Non input buffer ADC front end matching network topology
Because the equivalent internal resistance of ADC varies with frequency and deviates from the ideal high resistance state at high frequency, the selection of load impedance at the ADC end of anti aliasing filter is particularly important. The ideal ADC supports arbitrary selection of anti aliasing filter load, with no requirements at all. However, due to the change of internal resistance, in reality, ADC hopes that the load impedance of the front-end anti aliasing filter can be relatively small, that is, in the design of traditional 50ohm anti aliasing filter, the internal resistance of the kohm level of ADC can be ignored relative to 50ohm. But now more and more anti aliasing filters need 100ohm load design to achieve the optimal working state of the front-end drive stage. Fig. 5 takes the DVGA lmh6521 commonly used in the design of wireless base stations as an example. In order to achieve the optimal linear performance of the whole receiving link, it is recommended to use an anti aliasing filter of 100ohm. At this time, if the simple 100ohm load is still connected in parallel at the input end of the ADC, the non ideal characteristics of the internal resistance of the ADC will become more and more obvious with the increase of the input signal frequency and the widening of the input signal bandwidth. It will directly pull down the 100ohm load on the ADC side and deteriorate the in band flatness of the signal.
Fig. 3 Schematic diagram of load requirements under optimal working state of DVGA
In order to unify the design of anti aliasing filter to simplify its transplantation in different platform projects, it is expected that the ADC side (including ADC equivalent internal resistance and front-end matching circuit) will show consistent impedance characteristics in the whole signal bandwidth, such as 100ohm in the application of Fig. 3. The ADC front-end matching network is introduced, as shown in Fig. 4.
Figure 4 topology diagram of non input buffer ADC front-end matching network
among
1) R1 and R2 are the main components of ADC side impedance. Assuming the ideal high resistance characteristics of ADC, they represent the load on ADC side. Due to the limited internal resistance of ADC and the required matching network, in order to achieve the overall effect and still maintain the load state of 100ohm, R1 and R2 are much higher than the optimal value of 50ohm. R1 and R2 not only determine the actual common mode voltage of ADC input pin (VCM analog input common mode current * R1, ADC performance SNR and SFDR will change slightly with the change of VCM, see datasheet Figure 22); Moreover, it was originally the low resistance discharge path of sampling glitch, so it should not be too large. The value of R1 and R2 shall be the minimum value under the premise of realizing the combined load target at ADC end, and the maximum value shall not exceed 100ohm.
2) R5 and R6 represent the damping resistance of 5ohm or 10ohm connected in series at the ADC input port in order to attenuate the oscillation that may be caused by the parasitic inductance of bonding wire.
3) The network composed of r3-l1-l2-r4 is mainly responsible for in band flatness adjustment in UWB applications. Its significance lies in that the network is inductive and the impedance increases with frequency; It changes in the opposite direction to the equivalent internal resistance of ADC decreasing with frequency. The two terms are connected in parallel to keep the overall impedance unchanged within the required frequency range. If you think the network is too complex, you can also consider combining L1 and L2 into one inductor to disconnect the VCM; Considering that the separation of two inductors is only to provide a path parallel to R1 + R2 for VCM current, so as to reduce the offset of VCM from the ideal value.
4) The network composed of r7-l3 / / c1-r8 is mainly responsible for absorbing the sampling glitch. In the application of 50 ohm load anti aliasing filter, the 50 ohm load path is equivalent to the low resistance discharge path of sampling noise, so the selection of R-L / / C-R circuit can generally not be added. However, when the load impedance of anti aliasing filter increases, such as the application of 100 ohm anti aliasing filter mentioned above, R-L / / C-R network is recommended to be used in applications with high performance requirements. The sampling noise is caused by the switching of the sampling switch. Only by directly introducing a low resistance path at the ADC input pin can it be effectively absorbed, which is why the rlcr network needs to be as close to the ADC input pin layout as possible. Otherwise, the sampling noise will be transformed into noise affecting the performance of ADC under the action of dither, so as to deteriorate SNR and SFDR. The most important component of the sampling noise absorbing circuit is the capacitor, and the sampling noise is mostly composed of high-frequency components, forming a low resistance path, i.e. low-pass circuit or band-pass circuit (high resistance for useful signals and low resistance for high-frequency noise). The value of C is not easy to be too small, which will affect the absorption effect. Similarly, it is not easy to be too large, which will seriously affect the input bandwidth. The R in series at both ends is not easy to be too large, and it is better to be 25 Ohm. The inductance in parallel is mainly to reduce the Q value, which is helpful to flatten the in band fluctuation. When r3-l1-l2-r4 and r7-l3 / / c1-r8 networks coexist, L3 needs to be removed to form an r-cr network for the sake of in band flatness.
Simple value taking steps and principles:
1) If it is a traditional 50ohm anti aliasing filter design, R1 and R2 take 25ohm respectively, without adding r-l-l-r network, RL / / C-R network is optional.
2) In case of anti aliasing filter design of 100ohm and above. The receiving link needs to join R-L / / C-R, and the r-l-l-r network is optional (when r-l-l-r is optional, R-L / / C-R needs to be replaced with r-c-r); R-l-l-r needs to be added to the feedback link.
a) First, select R-L / / C-R or C in r-c-r network according to the performance test results. Taking H40 as an example, the RL / / C-R network C takes 10PF and the r-c-r network C takes 3.3pf, which can effectively filter the high-frequency sampling switching noise (in applications where the if is less than 350MHz). The R in the network should be 25ohm, and the principle of L in the network is to make the LC resonator form a resonant frequency near the center of the useful bandwidth.
b) Then, taking R1 and R2 as 100ohm respectively as the simulation starting point, the value of r-l-l-r is selected for the purpose of in band flatness. When the flatness meets the requirements, try to reduce the values of R1 and R2, but it is necessary to appropriately increase the equivalent impedance of r-l-l-r as compensation. Finally, find the minimum values of R1 and R2 on the premise of realizing the combined load target at the ADC end.
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Published at 08:45, April 4, 2018
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