AMD recently held a technical conference, the first disclosure of the Zen CPU architecture design, and publicly showed the same frequency 8 core 16 threads can be drawn from Intel Core i7-6900K. However, at the time, the architecture only talked about some cases, and now at the Hot Chips 2016 conference, AMD has announced many of the details of the ZEN architecture in the first time, how to explain 40% of the improvement of 40%. First, the so-called 40% improvement refers to changes in actual performance, but a change in the atrial indicator of the number of instructions per clock cycle (IPC), and the contrast object is the current Excavator excavator architecture.
This is some specific improvements in the ZEN architecture in performance, energy consumption, in which core engine improvements include: each core supports two logical threads, branch mistakes, improve, better branch prediction, larger operation cache, wider micro Directive assignment, larger integer / floating point command scheduler, larger rollback, larger rollover / load / storage sequence.
The cache system has a first-level cache write back, faster secondary / three-level cache, faster floating point unit load, better level / secondary data prefarable, first-level / second cache bandwidth improvement approaches 1 Double, the total bandwidth of the three-level cache is up to 4 times.
In order to reduce power consumption, the Zen architecture is also a lot of work, and the whole process uses low-power design concepts, including multi-hierarchical clock gall, first-level cache writing, larger operation cache, stack engine, etc..
Core Micro Architecture Details: Pick up four x86 instructions, operate cache instructions, four integer units, two storage / load units (support for 72 seminal loads), two floating point units (128-bit fmac), 4 -way 64KB level instruction cache, 8-Way 32KB level data cache, 8-way 512KB level cache, 8MB shared three-level cache.
Instruction picking part
Decoded part
Executive part
Load / storage unit and secondary cache
Floating point unit
Cache
CPU Complex (CCX): This explained this yesterday. The Zen architecture although every four cores are a group, this four cores do not have any other associations except for the shared levels, they are completely independent of each other.
Synchronous Multi-Thread (SMT): All instructions only support single-threaded mode, front-end queue divide priority, in addition to micro-instruction queues, retreat, and most of the modules outside of the storage queue are completely shared.
Add inventory set: ADX (extended multi-precision algorithm), RDSEED (Supplementary RDRAND random number generator), SMAP (Advanced Mode Access Interception), SHA1 / SHA256 (Hashgi Algorithm), CLFushopt, Xsavec / Xsaves / XRSTORS, CLZERO (Clean the cache line), PTE coalecing (4K page merges into 32K pages), where the last two are unique to the AMD ZEN architecture.
Continue to support all standard instructions: AVX, AVX-2, BMI1 / 2, AES, RDRAND, SMEP.
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