Lei Feng network news, as the communication industry gradually moved closer to 5G standards, mobile equipment manufacturer's ten minutes of technical test and concept verification test. Now, commercial feasibility of these technologies is carrying out strict assessments, however, many technologies used by prototype design are well transformed into commercial deployments.
To accelerate the solution of 5G deployment, shortly, Xilinx announced its next generation Zynq UltraScale + RFSOC single-chip adaptive radio platform, using TSM 16NM process, RF signal chain, ADC, DAC, Mac, DSP, radio IP, baseband, modulation Filter, and DDR4 memory subsystems are integrated into the SOC, replacing the discrete data converters by replacing the discrete data converter with integrated direct RF sampling techniques, and can reduce power consumption and package size of 50 ~ 75%.
According to the news released by Xilinx, one of the advantages of RFSOC is the radio of Massive-MIMO (large-scale antenna technology) for wireless networks. According to reports, 64x64 mimo using RFSOCS will reduce power consumption to reduce power consumption by 75%, and the number of components in the system is reduced by 89%.
Xilinx's RFSOC family has been developed to the three generations. The earliest first product covers 4GHz bands, supporting the DOCSIS 3.1 specification, making some 5G implementation-based positioning capabilities.
This release is the second generation and third generation products, of which the second generation chip is the first generation of fine-tuning enhancements, integrated quad-core Cortex A53 and dual-core Cortex A5 CPU with programmable module, covering 5GHz band, make China and Japanese markets can quickly start deployment.
The third generation of products still use similar underlying hardware, but upgraded ADC and DAC, can support 6GHz on different clock domains, and improve the running frequency of the programmable module to match the extra DSP demand brought by 6GHz. And 14bit processing accuracy, and in external clock generator mode, the number of clock generators needed throughout the design is also reduced from 4 to 1.
Xilinx said that one of the traditional design methods is that the interface between the RF sample discrete DSP and the digital front end is the JESD204 standard, in the 16x16 antenna solution, this standard interface is about 320GB / s bandwidth For 8W, this is a very power consumption when analyzing 800 MHz high frequency spectrum.
The third generation RFSoC product is integrated with the analog components, which can achieve a higher transmission bandwidth at lower power consumption. This will reduce the power consumption of TDD mode and provide complete multi-band / multi-standard support, and its integrated analog / digital solution also helps extend MMWAVE's intermediate frequency implementation.
Xilinx declaration allows first-level suppliers to use their custom programmable IP with RF, while secondary suppliers can use their own or fixed IP solutions. With this design, Xilinx can add RF markets to its product combination.
Both the second generation and the third generation RFSOC will be compatible with the first generation of hardware. The second-generation RFSOC's engineering sample is now available for customers. It is expected to be fully produced in June 2019, and the third generation RFSOC will be in 2019. Sampling in the second half of the year, in the third quarter of 2020, which will cover all unauthorized sub-6GHz bands in one chip.
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Original link: https://www.eeboard.com/news/xilinx-3/
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