Altera Company and T $ T $ T $ T $ T $ T $ T $ T $ T $ 20

Altera Company (NASDAQ: ALTR) and T $ T $ T $ T $ 1, working with TSMC's patented fine-distance copper bump packaging technology to build 20nm Arria® 10FPGA and SOC, Altera companies, become the first advanced Companies in mass production, successfully enhance the quality, reliability and efficacy of its 20nm device series. Bill Mazotti, Vice President, Altera Global Operation and Engineering, said that Taixiao provides a very advanced and highly integrated package solution to support our Arria 10 device, which is the industry's highest density 20nm FPGA single-chip. This package technology not only brings considerable assistance to Arria 10 FPGA and SOC and assist us in solving the challenges faced in 20nm packaging technology. Compared to the general standard copper bump solution, TSUA's advanced Crystal Game Array (FLIP CHIP BGA) package technology provides more excellent quality and reliability of Arria 10 devices in detail, this technology can be Meet the demand for high-performance FPGA on multi-bump contacts, also provides better bump welding point fatigue life, and improve electric migration and ultra-low dielectric dielectric layer (extra low-k layer) Low stress performance, these are very critical features for products produced using advanced silicon wafers technology. David Keller, senior deputy general manager of Taizhou Company, Northern US Subprint, said: Taizhou copper bump packaging technology creates excellent value for the use of ultra-low dielectric materials and advanced silicon wafers that require microclural (less than 150 microns) bumps, We are very happy that Altera adopts this highly integrated package solution. Altera now launches Arria 10 FPGA produced by T $ 20Soc process and its innovative packaging technology. Arria 10 FPGA and SOC have the highest density single-chip in the FPGA industry, which is more than 40% of the new series of components than the previous 28nm Arria series. Tajigin Company copper bump packaging technology is suitable for large-size chips and fine spacing products, including TSMC Manufactureability Design (DFM) / Reliability Design (DFR) Practical Tools, able to assemble more The process parameters range and high reliability are adjusted by packaging design and structures, and the production stage assembly yield of this technology is better than 99.8%. Related Reading: Altera and Intel have further strengthened cooperation, develop multi-pipe core devices Altera teamed up with Intel to preempt the process market, Xilinx's positive war Altera launches a single-chip implementation of integrated PLC and HMI system Altera Open Source MAX® II Development Kit Altera will cooperate with Intel to make 64-bit ARM SOC adopt the latest 14-nanometer craftsmanship

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