The timing / counter has a function of timing or external event count. Typically, the timing / counter is generally three types:
The hardware counter can count under simple software control, which is low cost, easy to use, but strong dedicated, not wide. Be
The software timing / counter feature is hardware cost, but he occupies the runtime of the CPU and reduces the work efficiency of the CPU. Be
Programmable timing / counter features are flexible, and do not occupy the runtime of the CPU, the disadvantage is costly. Among them, programmable timing / counter 8253 is a relatively universal programmable timing / counter. Be
The programmable timing / counter 8253 can generate various time delay signals, and his use is very wide, usually used for timing control, delay, counting, etc., such as timing refresh RAM, system clock timing, speaker Pronunciation length control. It is necessary to perform tight calculations and precise tests to meet different requirements. Be
1 Working principle of programmable timing / counter 8253
Programmable timing / counter 8253 is a large scale integrated circuit made of an NMOS process, and different functions can be achieved by simple programming, and FIG. 1 is a basic schematic of programmable timing / counter 8253. Be
As can be seen from Figure 1, there are 3 independent counters in the chip, which are counter 0, counter 1, counter 2, each counter is 16 bits, and can set a working mode for them (by control word settings) ). Be
Figure 2 is a 8253 pin diagram after the package.
Programmable timing / counter 8253 can be applied in two cases: timing, count. When used as a timer, you can cycle count, the source source is generally the system itself; when used as a counter, the signal source is generally a system file. In the speaker drive system, the programmable timing / counter 8253 is used by the timer. Be
The meanings of the corresponding pins in Figure 2 are as follows:
CLK0, CLK1, CLK2: The clock input of the counter. Be
Gate0, Gate1, Gate2: The counter output signal is output. Be
OUT0, OUT1, OUT2: The counter output signal is output. Be
RD: Read the signal. Low level is valid, read the count value of the counter to the buffer. Be
WR: Write signal. Low level is effective and receives data sent by the buffer. Be
CS: chip select signal. Low level is effective. Only when the CS signal is low, the read / write operation can be generated, otherwise it will not be read. Be
A1 ~ A0: Add 3 counter and 1 control register port. Be
D7 ~ D0: mode control word. The programmable timing / counter can work correctly, closely related to mode control. The way the control format is as follows:
Mode control word to see the data manual. Be
VCC: +5 V Power. Be
GND: Ground pin. Be
2 Application of programmable timing / counter 8253 in a speaker
The hardware composition of the speaker drive system is shown in Figure 3. The driving signal is issued by the 8253 drive speaker vocal as a peripheral circuit 8255 on the system insert. SPK DATA and TIM GATESPK are connected to the output port of 8255 in Figure 3. Where TIM GateSPK controls 8253 timers to drive speakers, SPK DATAs to control the door circuit of the speaker. It is more difficult to listen directly from the door circuit drive, and it is better to listen more, so it is best to add a filter as shown in Figure 3 by filtering off the clutter. Be
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(1) First, the process of using the speaker is first described in the flowchart, as shown in Figure 4.
(2) Programmable timing / counter 8253 programming in the speaker. In general, the output port address of 8255 is 61h, the control port address assigned to 8253 is 46 h, and the three counter port addresses are 40 h, 42h, 44h, and the counter 2 operates in mode 3, and 8253 can be used as the timer. Drive the speaker vocal. Be
Then the writer is as follows:
From the program, you can see that the use of programmable timing / counter 8253 can issue a variety of frequencies, as long as it is slightly changed in the program to the input clock frequency or the initial value can be implemented. Read more
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