introduction
With the development of mobile communication technology, the study of RF (RF) circuits has attracted extensive attention. The standard CMOS process implements the voltage controlled oscillator (VCO), which is the key to implementing the RF CMOS integrated transceiver. Most of the VCO circuits use a reverse biased container diode as a voltage control device, however, when the circuit is implemented with the actual process, it is found that the quality factor of the container diode is usually small, which will affect the performance of the circuit. As a result, people try to use other devices that can be implemented with the CMOS process, replacing the general container diode, and the MOS becoming tube is born.
MOS variable pipe
The drain, source and substrate of the MOS transistor can be short-line, and the capacitance value varies with the voltage VBG between the gate and the substrate. In the PMOS capacitance, the reverse carrier channel is established when VBG is greater than the threshold voltage, and when VBG is much greater than the threshold voltage, the PMOS capacitance operates in a strong reverse region. On the other hand, when the gate voltage Vg is greater than the substrate voltage Vb, the PMOS capacitance operates in the accumulation zone, at which time the interface voltage between the gate oxide layer and the semiconductor is positive and the electrons can be free to move. Thus, the PMOS capacitance value CMOS of the invertoff area and the accumulation zone is equal to Cox (oxide layer capacitance).
There are also three working regions between strong flying regions and accumulation zones: medium-retrorefront, weak, and depleted areas. There are only few mobile carriers in these working regions such that the CMOS capacitance value is reduced (smaller than COX), and the CMOS at this time can be regarded as a parallel capacitor of COX and CB and CI. CB represents a closed loop depleted region capacitance, and Ci is associated with the amount of varying amounts of the gate oxide interface. If CB (CI) dominates, the PMOS device works in a depleted (medium and reflex) zone; if the two capacitors do not dominate, the PMOS device operates in a weak array. The CMOS capacitor value is shown in Figure 1 with the curve of VBG changes.
The channel parasitic resistance value of the PMOS working in the strongly-flex zone can be drawn by the following formula:
(1)
In the formula, W, L and KP are the width, length, and gain factors of the PMOS transistor, respectively. It is worth noting that as the VBG is close to the threshold voltage, the RMOS is gradually increased, and the RMOS is infinite when the VBG is equal to the threshold voltage. This formula is based on a simple PMOS model. In fact, with the steady reduction of the hole concentration, the RMOS will maintain a limited value throughout the container.
Reverse and accumulated MOS variable pipe
Through the above analysis, we know that ordinary MOS becoming tube tuning features are non-monotonous, there are currently two ways to get monotonic tuning characteristics.
One method is to ensure that the transistor does not enter the accumulation zone in the case where the VG variation range is large, which can be done by interrupting the substrate to the gate source and the DC voltage in the circuit is done (eg, the power supply voltage VDD).
Figure 2 is a mutual contrast of the CMOS-VSG characteristic curve of two identified MOS capacitances.
It is clear that the tuning range of the MOS capacitance is wider than the ordinary MOS capacitance. The former works only in strong, neutralized and weak, and never enter the accumulation zone.
A better way is to apply only MOS devices that work only in the exhausted area and accumulation zone, which will bring a larger tuning range and have a lower parasitic resistance, which means that a higher quality factor is due to its exhaustion. Electrons of the district and accumulation zone are multi-carriers, more than three times higher than the mobility of holes. To get an accumulated MOS capacitor, you must ensure that the strong inverting area, the inverting area, and the weak inverter region are prohibited, which requires suppressing any holes to inject MOS. The method is to dopase p + doping of the drain in the MOS device, while the N + doped substrate contact is made in the position of the original drain, as shown in FIG.
This reduces the parasitic resistance of the N well. The tuning curve of accumulated MOS capacitors and ordinary MOS capacitors is shown in Figure 4.
It can be seen that the accumulated MOS capacitance is good. It is worth noting that no additional process flow is not introduced during the design of the accumulated MOS capacitance.
Design and simulation results
The VCO circuit structure used by the author is shown in Figure 5. This is a standard symmetric CMOS structure, two paragraph tube symmetrical connections, reduced the effects of potential changes on the varying tube capacitance value at both ends, and improved spectrum purity. In order to ensure that the match is good, the inductance should be used in the same dual inductor symmetrical connection. In addition, since the LC oscillation loop is composed of two dimensions, the integrated MOS variable tube is equipped with both large size, the higher loss makes the quality factor, which requires a larger The negative hurdles maintain the oscillation continuous; and the equivalent negative transconductance must be larger than the cross-guided value required by the maintenance equal oscillation, so the two pairs of coupling transistors need to set a larger length ratio, but Large length ratio also brings a large parasitic effect, causing phase noise and tuning range to affected, and finally form a negative resistance in two NMOS transistors to compensate for the loss of VCO. According to the small signal model analysis, various parasitic and high-order effects can be estimated to be estimated to obtain an equivalent negative resistance RG is (set two active device transconductive to GM1, GM2):
(2)
The top PMOS transistor provides a bias current, and the power supply voltage required for this structure is very low.
The entire design based on the 0.35μm germanium radio frequency process model PDK in TSMC, a three-layer metal. Among them, inductance is a flat spiral octagon, which is wound by the top metal. The selection of the inductance value is 0.6 nh, then the total capacitance size can be determined if the oscillation frequency is selected. The capacitive component constituting the LC oscillation loop has an inductive parasitic capacitance (small), the drain-substrate capacitance of the NMOS transistor, a grate-leakage capacitor, a gate-source capacitor, and an important accumulation MOS capacitor. In the case of ensuring the spree, in order to obtain a larger tuning range, a proportion must be as large as possible.
The power supply voltage is 1.5V, and the power consumption is about 10 mW. The simulation is performed with the SpecTrerf under the Cadence platform, and the resulting tuning curve is shown in Figure 6. When the control voltage is changed from 0 to 2V, the oscillation frequency varies between 3.59 to 4.77 GHz, the center frequency is 4.18 GHz, and the tuning range is approximately 28%. The phase noise curve at the center frequency is shown in Fig. 7. At this time, the control voltage is 0.75 V, and the phase noise of the corresponding offset is 600 kHz is -128 dB / Hz.
When the control voltage becomes 0.75 V to 2V, the oscillation frequency becomes 4.77 GHz, and the phase noise becomes -135 dB / Hz, which is reduced by 7dB. This is caused by two reasons, first because the total capacitance of the LC oscillation loop is reduced, the oscillation frequency increases, which reduces the negative cross guide required to maintain oscillation, but because two NMOS transistors are provided. The negative gang is almost unchanged, so the stable oscillation is increased, and the phase noise is reduced. On the other hand, the channel parasitic resistance of the accumulated MOS capacitance from this process will be reduced as the voltage is increased, thereby reducing the loss and reduces phase noise.
Compared to the VCO designed by the reverse MOS velocked tube, since the electron has a high mobility, the channel parasitic resistance of the accumulated MOS capacitor is lower than the reverse MOS capacitance, that is, the accumulated MOS capacitance has high The quality factor has led to an increase in the overall performance of VCO, especially the phase noise decreases. The comparison results are shown in Table 1. Considering factors such as processes and power, there is a greater advantage of accumulating MOS capacitors.
in conclusion
Based on 0.35μm process, a VCO having a working frequency of 4.2 GHz is designed, and the accumulated MOS capacitance and the reverse MOS capacitor are tuned in this circuit. The simulation results show that the range of the two VCO tuning is almost the same, and when the power consumption is about 10 mW, the accumulated MOS tuning VCO exhibits better phase noise performance.
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Source: Wiku Electronic Market Network
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