MOSFET is widely used as a power switching element to a regulator and a motor controller. In various H-bridge configurations, they can not only be integrated into ICs.
A high side (HS) power MOSFET, M1, and a low side (LS) MOSFET, M2 are used to drive inductive load (Fig. 1). When the HS FET is turned on, when the LS FET is turned off, the current from the power VCC flows out of the inductance L0. When the HS FET is turned off, the LS FET is turned on, the inductor current continues simultaneously from the zero point.
When the HS and LS power fet are turned on, the so-called breakdown of the severe short-circuit occurred. Even if we have never intended to turn on both FETs, it is also possible to break through. For example, when the instruction turns on the HS FET, when the LS FET is turned off, the logic propagation is delayed. When the HS FET is half open, the LS FET is half turned off, and the door capacitor to the FET is charged or discharged requires a shorter time. If so, the current flows directly from the VCC through two FETs into GND (breakdown).
In Figure 1, we are embedded in the half H bridge topology for the design of the automatic failure MOSFET breakdown protection. The HS_ON signal is turned on and off via the HS drive, which is generated by a digital microcontroller or by a feedback loop containing a comparator or error amplifier.
The HS driver converts the low power logic horizontal signal to a high power HS_ON signal. Similarly, the LS_ON signal is turned on and off through the LS driver. The circuit controls the motor system or three-phase regulator by making two power MOSFETs with the correct order.
This protection configuration automatically detects the conductive status of the HS and LS FETs. The HS FET is prohibited from turning on unless the LS device is completely closed. Our counterattack design fully protects the MOSFET H bridge during normal operation, and there is a number of noise interference or error control programs in the system to ensure the operation of automatic failure.
In order to turn on the HS FET, the system sets the signal HS_ON to a high value. This design is like this: if the LS FET is turned off (after this later), HS_EN is a high value. The HS_ON high value causes the output terminal Qz (LS_EN) of the lock LSR0 device to a low value, so that the LS FET does not work. The HS drive is also required to open it by the gate and source (VGS) through the HS FET with a voltage.
Through the HS VGS monitor to detect the opening state of the HS FET, the signal detection of HS_IS_ON is high, and the LS_EN_RST remains a low value. The final result is LS_EN to keep a low value without allowing LS FET. As long as the HS FET is turned on, the LS FET can not be run. In order to make this configuration, HS_ON must be used for NOR gate (NOR0) input. This ensures that the LS_EN will keep a low value as long as HS_ON is high.
Under normal conditions, HS_ON and HS_IS_ON are sufficient to keep the LS FET close when the HS FET is ready to open or turn on. In practical applications, noise interference (or system errors) often generate small faults in the control signal, due to the limited response time of the drive and VGS monitors (logical type), so that HS_IS_ON is unreliable (VGS monitor invalid). In this case, LS_EN_BLANK guarantees the operation of the automatic failure, as described below.
Each HS_ON is turned from a low value to a high value, an edge detector (R0, C3, and 4) generate a short period of 20-NS pulse to turn on M0, start a pulse cycle (M0, C2, INV0), Outputs a 150-NS LS_EN_BLANK pulse to keep the LS_EN at a low value of 150ns. In this 150NS, any operation attempts to turn on the LS FET is an abnormal unsafe operation. Therefore, the LS FET is stably closed. I3ua is a 3- for charging C2? A current source. Due to the 20NS short contact, 150ns is again triggered again. This ensures that the protection circuit can operate normally even in the case where there is a multi-interference small fault on the HS_ON line.
Jumping We use 150ns as an example, in general, a pulse cycle must be longer than the HS VGS monitor and HS driver, including total signal propagation delays in all parasitic components contribution. However, this cycle is shorter than normal HS_ON pulse width to avoid the normal operation of the interference. For the stability of the system, the noise in the control loop is filtered by the lock LSR0 as the low pass filter.
In Fig. 2, the first column of the signal (left) is indicated normally. The signal name corresponds to FIG. 1. When HS_ON is high, the command drive turns on the HS FET, HS_FET_G-HS_FET_s rises. After the monitoring circuit detects, the HS_IS_ON correctly displays the LS FET (LS_EN is low) until the HS FET is completely closed (HS_FET_G-HS_FET_S close to zero).
The second column (right side) of the signal indicates abnormal operation. When the HS_ON instruction is too early due to noise or firmware failure, the HS FET is in a semi-open state. The HS monitor cannot detect this HS FET in turn on, because its limited response time, so it incorrectly displays HS_IS_ON to a low value. Without ls_en_blank, the LS_EN signal will be high, allowing the system to turn the LS FET halfway at HS FET. Due to the LS_EN_Blank pulse, LS_EN maintains a low value of 150ns, allowing the HS FET gate voltage to be set to a low value between LS_EN. Results Avoid breakdown.
Out of simple, Figure 1 saves the circuit block that drives HS_EN. Simply use the same circuit to issue an LS_EN signal monitoring LS_FET_G, and the LS_ON signal generates an HS_EN signal.
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