The decimal frequency synthesizer must take an external loop filter circuit and a voltage controlled oscillator to form a complete phase-locked loop circuit. A peripheral circuit in the loop filter design will directly affect the performance of the test chip. Taking the ADF4153 decimal frequency synthesizer as an example, the design method of its peripheral loop filter is studied, which gives a loop filter design process based on chip testing, and tests testing.
The test results show that the filter meets the need for decimal frequency synthesizer chip test. When performing a chip test of a decimal frequency synthesizer, the digital portion can be achieved by a conventional digital test method; and the phase noise of the radio frequency signal is output, and the stray noise requires the chip to work in a normal output. The decimal frequency synthesizer chip requires an external loop filter (LF), and the voltage controlled oscillator (VCO) can constitute a complete lock-phase loop circuit, which can be implemented in the premise of normal chip functionality. Phase noise, test under spurious noise.
In general, the voltage controlled oscillator uses ready-made devices that pay attention to performance indicators when selecting devices, only loop filters are required to be calculated and designed. The loop filter is mainly used as a low-pass filter throughout the circuit, which performs low-pass filtering of the pulse signal output by the chip detector, filter the high frequency component, and finally obtains a relatively smooth DC voltage signal to control the VCO. work, so as to obtain a stable frequency output. The performance of the loop filter will directly affect the performance of the decimal frequency synthesizer chip.
In this paper, the ADF 4153 decimal frequency synthesizer is used as an example, and the design method of the third-order loop filter is given, and the needs of the actual test of the chip can be satisfied.
Design of external loop filters
The loop filter is an important part of the charge pump locking loop circuit, which is connected between the charge pump and the voltage controlled oscillator. The basic frequency characteristic of the phase locked loop is determined by the loop filter. In fact, it is because of the presence of loop filters, the phase locked loop can be selected within any central frequency and bandwidth. The type of loop filter is widely divided into two major classes of the active filter and passive filter, and the passive filter is similar to the active filter, which is the advantage of: the structure is simple, low noise, high stability. Degree and easy to implement.
A common passive filter is a three-order filter shown in Figure 1. In general, the bandwidth of the loop filter should be 1/10 of the PFD frequency (channel interval). Improve loop bandwidth reduces the lock time. However, the loop bandwidth has greatly increased the unstable in the conference, resulting in a state in which the phase locked loop cannot be locked.
Figure 1 Three-bound loop filter
Loop filter design parameters
In order to study the influence of the loop filter to the phase noise of the phase-locked loop output frequency, the peripheral loop filter required for the chip test is designed. We have made the following simulation configuration in the AdisimPLL software. Device Model: ADF 4153, FPFD = 25MHz (ideal Signal), INT = 69, FRAC = 101, MOD = 125, VCO uses Zcomm's V674ME34-LF, and under this configuration, RFOUT = 1.7452GHz is expected.
A) Set the loop filter bandwidth of 20 kHz, phase margin 50 °, the simulation of its phase noise is shown in Figure 2.
Figure 2 Phase noise simulation chart at 20 kHz of loop bandwidth
From Fig. 2, it is possible to know that when the loop filter bandwidth is 20 kHz, the phase noise caused by the VCO occupies dominates. The phase noise caused by the chip is submerged under total output noise. In other words, when the loop bandwidth is narrow (such as 20 kH), the phase noise test is performed for the phase-locked loop output signal, and the result cannot truly reflect the phase noise output from the chip.
Figure 3 Loop filter and RF circuit design
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Source: Wiku Electronic Market Network
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