Key words:
ADSP-BF561, encoder
The bandwidth of the Internet is increasing, and the Internet-based information, especially the transmission of real-time data in sound images, has become possible. The transmission of video and audio data is just fully utilizing Internet bandwidth, and achieving real-time communication and possibly possible. Video conferencing systems is more fully utilizing Internet resources than traditional conference prices, thereby reducing operating costs.
The video encoder is the main component of the video conferencing system. At present, the video compression standard has H.261, H.263, MPEG4 and H.264, etc. The new generation of video coding standard H.264 has the advantages of high compression ratio compared to previous standards, good network affinity, superior video quality. H.264 introduces a number of new technologies in current video coding, so that under the same reconstruction image quality, the encoded efficiency is about 50% higher than H.263 and MPEG-4. Therefore, the video encoder design uses H.264 coding standards, and the encoder is mainly achieved by the US AD's BF561 DSP chip. At present, the video processing plan has also been turned to the DSP platform by the ASIC scheme previously year. The development of video product development on the DSP platform has the following advantages: First, the user has more freedom of development, supporting a variety of personalized development, can adapt to the new requirements of the market, improve product performance in the first time, enhanced The competitiveness of the product; the second, DSP processing ability is strong, can achieve multiple channels, compression processing of multi-channel, video signals on a DSP; third, short development cycle, can achieve fast technology update and product replacement, various new emergence The fast and optimization algorithms can be upgraded flexibly.
1 bf561 introduction
The BF561 adopts a symmetric dual-core architecture, 2 BF533 DSP kernels are integrated inside a BF561 chip, and 2 cores can be up to 600 MHz, support parallel processing. The characteristics of the BF561 processor guarantees its powerful digital signal processing capabilities, and supports low-voltage low current power supply to meet multi-function digital consumer products for performance, power consumption requirements.
1.1 DMA introduction
The Blackfin processor uses direct memory access (DMA) between memory or data between the memory and the peripheral. DMA controllers can perform data transfer between memory and on-chip peripherals (peripheral DMA), and data transfer (memory DMA or MDMA) between L1 / L2 / L3 memory. The DMA controller is an important component in the Blackfin processor architecture. It is completely independent of the kernel, and does not perform cycle misappropriation, and does not require the processor core cycle. In an ideal application configuration, the kernel only needs to set the DMA controller and respond to the interrupt during the data call.
BF561 has 3 separate DMA controllers DMA1, DMA2 and IMDMA. DMA1 and DMA2 controllers have 12 peripheral DMA channels and 4 memory DMA channels. The IMDMA controller has four memory DMA channels.
1.2 DMA based on descriptor
The descriptor-based DMA transmission requires the parameters stored in the memory to initialize a DMA queue. The descriptor includes all parameters that need to be programmed normally to the DMA control register. The descriptor allows multiple DMA queues to be linked together. In a descriptive DMA operation, a DMA channel can be programmed to automatically set and activate other DMA transfer processes after completion of the current transfer queue. When managing a system's DMA transfer process, the descriptor-based model provides maximum flexibility.
The descriptor list model is divided into a list "small" mode and descriptor list "big" mode. In the descriptor list "small" mode, the description segment includes a 16-bit field to indicate the lower 16 bits of the next descriptor inlet address, and the high 16 bits of the address are obtained by the register and remain unchanged, and the descriptor is A specific 64 kb size page of the memory. When the descriptor needs a cross page, you can use a list of descriptor lists that can provide a 32-bit entry address.
2 H. 264 video encoder composition
H. The 264 encoder consists of video acquisition, data format conversion, H.264 encoding 3 part. The video acquisition portion is responsible for capturing images and pops the captured image into the specified video frame buffer through the PPI interface. The data format conversion section completes data that converts the image of the 4: 2: 2 format of the input to the H-264 encoder to encode data of 4: 2: 0 format. The H.264 encoding part is responsible for the 4: 2: 0 format image encoding.
In this video encoder design, the BF561 A is used to run the operating system and protocol stack, and the H.264 algorithm is implemented in B.
2.1 Video Collection
Video acquisition is completed by the camera OV7660, and OV7660 is a CMOS color image sensor chip developed by Omnivision, USA, support VGA, QVGA, GIF and other resolutions. The video output format has RAW RGB, GRB 4: 2: 2 and YUV / YCB-CR (4: 2: 2). In this design, select the CIF YVYU (4: 2: 2) format, you need to set its corresponding register COML = 0x00, CLKRC = OX80, COM7 = 0x30, TSLB = 0x05. After the camera is configured, open the PPIO to populate the video data to the video frame buffer of the Blackfin processor. The ping-pong buffer can be easily achieved with a descriptor-based PPI DMA, ensuring that the input data that has not been processed is not overwritten.
The principle of ping-pong buffer is shown in Figure 1.
Set two CIF 4: 2: 2 frame size input buffer, first input data to 4: 2: 2 video frame 1 via the PPI interface, the processor performs the frame data when the first frame data is filled MDMA movement and compression coding, etc., at the same time, the PPI continues to fill the second video frame. When the second video frame is filled, the processor processes the second video frame simultaneously fills the first video frame. With ping-pong buffering, data will continue to fill the source source into two video frames.
2.2 Data Format Conversion
The video captured image is the intertwined 4: 2: 2 format YUV video data, while the H.264 video coding algorithm is compressed by video data in 4: 2: O format. The luminance value buffer of the 4: 2: O format data is separated, and the brightness buffer and chroma buffer can be achieved by MDMA.
CIF YVYU (4: 2: 2) Format Data As shown in Table 1, CIF 4: 2: O format data is shown in Table 2. 4: 2: 2 Format Image There are 4 Y components, 2 u components, and 2 V components in a macro pixel. 4: 2: 0 Format Image There are 4 Y components, 1 U component, and 1 V component in a macro pixel. Y, U and V storage area are separated, y is before, then U, finally V.
Convert 4: 2: 2 format into 4: 2: O format, to keep all Y, and Take the U and 1, 3, 5 ... row V. Using MDMA based on descriptor list "big" mode, three pairs of descriptors Source_Y, DEST_Y, SOURCE_U, DEST_U, SOURCE_V, DEST_V, the two descriptor layers of the source and destination, etc., for Y, U and V from interleaved 4 : 2: 2 Source Data Zone to Y, U and V Separation of the destination data area.
When a frame CIF 4: 2: 2 format data is filled into a video frame buffer of a Blackfin processor via PPI, an interrupt is generated, and the MDMA is activated in the interrupt processing subroutine, separating the brightness value and the chrominance value, and then handed over to H . The 264 encoder is encoded.
2.3 H. 264 encoding
After waiting for a frame 4: 2: O format data, perform H. 264 encoding, then continue waiting for the production of 4: 2: 0 format data until the encoding ends.
3 experimental results and analysis
In the experiment, the H.264 encoder encoded the image acquired by the camera and saved the compressed code in the form of a file in the local memory. After the encoding is over, use H. The decoder of 264 is decoded to the compressed code stream, and the decoded video file is played with YUVVIEWERPLUS.EXE.
In the experiment, the encoder can reach the speed of 15 frames per second. The image definition after decoding is basically the same as the image quality, and the image is very clear than the image of Image Viewer in VisualDSP ++ 5.0. The speed of the OV7660 acquisition image is 30 frames per second, and the H.264 encoder does not reach real-time encoding.
In the experiment, the BF561-based H.264 encoder did not achieve real-time coding is not to optimize H.264 open source code. Since the CIF format image data is relatively large, it is necessary to store in the external memory, the processor access external memory time is relatively long; the DCT and motion estimation calculation method are time consuming, with C language implementation; some auxiliary functions and print information, etc. Thereby affect the speed port of the encoder.
4 knot
B based on the BF561 H. The 264 encoder does not reach real-time encoding. Future work focuses on using the VisualDsp ++ development environment of the C compiler for code optimization; how to make full use of internal storage spatial resources and to reduce the internal and external data scheduling on system performance by DMA, cache, etc. Some system calls are more frequent, more time-consuming modules, such as DCT and motion estimates, take advantage of BF561's instruction set, realize the assembly language; go out of unnecessary auxiliary functions and print information in the source program to achieve BF561 H. 264 Encoder Real Time Coding.
As consumer electronics further enters ordinary homes, applying H.264 standard video conferencing, audio-visual calls, and unmanned monitoring systems will also get more and more extensive applications.
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