Moore's lawsuits for more than 20 years have gradually become signs of failure in recent years. From the manufacture of chips, 7 nm is the physical limit of silicon material chips. However, according to foreign media, a team of the Lawrence Burkeley National Lab broke the physical limit, using carbon nanotube composites to reduce the existing most precipitial transistor process from 14 nm to 1 nm. So why say 7nm is the physical limit of the silicon material chip, how is the carbon nanotube composite material? In the face of the technical breakthrough in the United States, what should China do?
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Moore's lawsuits for more than 20 years have gradually become signs of failure in recent years. From the manufacture of chips, 7 nm is the physical limit of silicon material chips. However, according to foreign media, a team of the Lawrence Burkeley National Lab broke the physical limit, using carbon nanotube composites to reduce the existing most precipitial transistor process from 14 nm to 1 nm. So why say 7nm is the physical limit of the silicon material chip, how is the carbon nanotube composite material? In the face of the technical breakthrough in the United States, what should China do?
Image Credit: Extremetch
| What is the concept of XX NM manufacturing process?
The manufacturing process of chips often uses 90 nm, 65 nm, 40 nm, 28 nm, 22 nm, 14 nm, such as Intel's latest six-generation Core series CPU uses Intel's own 14nm manufacturing process. The current CPU integrates a transistor in units of millions of transistors. This transistor is composed of a source, drain and a gate between them. The current flows from the source into the drain, and the gate acts as a control current. Role.
The so-called XX NM actually refers to the width of the complementary oxide metal semiconductor field effect transistor gate formed by the CPU, also referred to as a gate length.
The shorter the gate length, and more transistors can be integrated on the same size silicon-Intel once declared that the area of the transistor will decrease when the gate length is reduced from 130 nm to 90 nm, and the area of the transistor will be reduced by half; in the chip transistor integration In linear, use more advanced manufacturing processes, the smaller the area of the chip, the lower the cost.
The gate length can be divided into a lithographic gate and the actual gate length, and the radial radial gate is determined by the lithography. Since there is a diffraction phenomenon in photolithography and the steps of ion implantation, etching, plasma flushing, heat treatment in photolithography, thereby causing the radial gate length and the actual gate length inconsistent. In addition, the actual gate length will not be the same as the same process process. For example, although Samsung also introduces a chip of the 14nm process process, the actual gate length of the chip and the actual gate length of the 14nm process chip in Intel still have a gap.
| Why is 7nm a physical limit?
The length of the shortened transistor gate can be explained before the CPU integrates more transistors or effectively reducing the area and power consumption of transistors, and reduces the wafer cost of the CPU. It is therefore, the CPU manufacturer spares no effort to reduce the gate width of the transistor to increase the number of transistors integrated on the unit area. However, this approach will also shorten the distance from the electron movement, which is likely to cause the transistor internal electron to spontaneously flow from the negative electrode to the positive electrode through the silicon bottom plate of the transistor passage, that is, leakage. Moreover, as the number of transistors in the chip increases, the silica insulation layer originally only only atomic laminates will become thinner and causes leakage more electrons, and then the leakage current increases the additional power consumption of the chip.
In order to solve the problem of leakage, Intel, IBM and other companies can be described as eight fans over the sea, each showing. For example, Intel combines high dielectric thin films and metal door integrated circuits in its manufacturing process to solve leakage problems; IBM has developed SOI technology - buried a strong dielectric film in the source and drain to solve leakage problems; And the fin field effect electrical crystal technology is added to increase the capacitance value by increasing the surface area of the insulating layer, and the leakage current is reduced to prevent the purpose of preventing electronic jumps.
The above approach can effectively solve the leakage problem to a certain extent when the gate is greater than 7 nm. However, on the basis of using existing chip materials, once the transistor grid is less than 7 nm, the electrons in transistors can easily produce tunneling effects, which brings huge challenges for the manufacture of chips. In response to this problem, it is an effective solution to transistors for replacing the new material to replace silicon production of 7 nm or less.
| 1 nm process transistors are still in the laboratory phase
Carbon nanotubes and a very hot graphene in recent years have a certain connection, zero dimerene, one-dimensional carbon nanotubes, two-dimensional graphenes belong to the carbon nanomaterial family, and each other can be in the form Transformation. Carbon nanotubes are a one-dimensional material having a special structure. Its radial dimension can reach nano-stage, the axial dimension is micrometer, and the ends of the tube are generally sealed, so it has a lot of strength while huge The long-diameter ratio is expected to make the carbon fiber having excellent toughness.
Carbon nanotubes and graphene have similar properties in electrical and mechanics, there are preferred conductivity, mechanical properties and thermal conductivity, which makes carbon nanotube composites in supercapacitors, solar cells, displays, biodetes, fuel There is a good application prospect of battery or the like. Further, the carbon nanotube composite of some modifiers is also received widely, for example, adding a CDTE quantum dot to the graphene / carbon nanotube composite electrode to produce a photovoltaic switch, doped metal particles to produce a field transmissive device. The Lawrence Burkeley National Laboratory of foreign media reported the existing most precipitial transistor process from 14 nm to 1 nm, and its transistor was made from carbon nanotubes doped molybdenum sulfide. However, this technology achievement is only in the stage of laboratory technology breakthrough, and there is currently no capacity of commercial production. As for this technology, it will become mainstream commercial technology in the future, and it has to be tested.
Technology progress does not necessarily bring business interests
In the past few decades, due to the fact that Moore's law did play, China Semiconductor Manufacturing Technology was always pulled out abroad in the process of chasing the West. In recent years, the development of chip manufacturing techniques is slow, and the objective phenomenon of failure of Moore's law has a great advantage for China's semiconductor industry. Moore's law failure, on the one hand, both technical factors - advanced lightning machine, etching machine and other equipment and advanced chip manufacturing technology research and development technology difficult, high fund requirements ... There is also a business factor on the other hand.
Before the manufacturing process reaches 28 nm, every advancement of the manufacturing process allows chip manufacturers to get huge profits. However, after the manufacturing process reaches 14/16 nm, the advancement of technology will increase the cost of the chip - when Intel has first developed a 14nm manufacturing process, it is said that its mask cost is 300 million US dollars. Of course, over time and TSMP, Samsung masters 14 / 16nm process, the current price should not be so expensive. But Intel is being developed 10nm process, according to Intel's official estimation, the mask cost is at least $ 1 billion. The new manufacturing process is expensive. On the one hand, it is expensive to develop costs and low yields in new processes, and on the other hand, it is also because of the exceptions of equipment such as lightning machine, etching machine. Therefore, even if the advanced manufacturing process is technically mature, due to the excessive mask cost, the customer will cause the customer to think twice while choosing the most advanced manufacturing process, for example, if the output of the 10nm manufacturing process chip is less than 1000 Ten thousand pieces, then the mask cost on each chip is as high as $ 100, according to the international general low profit chip design company's pricing strategy 8:20 pricing method - which is the case of hardware costs 8, pricing 20, don't think this price is high, it is already very low, Intel general pricing strategy is 8: 35, AMD history has reached 8:50 ... Even if it is not wafer cost and test costs, this The price of 10 nm CPU will not be less than $ 250. At the same time, relatively small customers will lead to a huge production cost, and ultimately slow down the development and business applications of advanced manufacturing processes. It is also because the 28nm manufacturing process is considered very dynamic by some of the industry insiders, and it will continue to use for several years.
China should work hard to solve real problems
For the Lawrence Burkeley National Lab, the existing most precipitial transistor process is reduced from 14 nm to 1 nm, and the Chinese don't have to look too much, because this is just a technical breakthrough in the laboratory, even if it is referred to, The technology has been mature and commercialized. Because of its difficulty in commercialization, it is much more difficult to develop 10nm manufacturing process in Intel - the cost will be highly unrecovered, which will make it high in the price of the chip produced by the technology. This will lead to less customers to choose this technology, and thus vicious circle ... From commercial factors, most IC design companies may still choose relatively mature, or called relative "old" manufacturing process.
For the current China Semiconductor Industry, it is better to explore 7nm physical limits with its huge human and labor. It is better to improve the IP library of 28nm process technology and realize the commercial mass production of 14nm manufacturing process. After all, for the national defense security field, existing manufacturing processes have been fully enough (many military chips in the United States are still 65nm). For commercial chips, many chips are not high, like industrial control chips, Automotive electronics, radiofrequency, etc. are used in some hardware enthusiasts that look for old processes, and for PCs and mobile phones, Tablets CPU, GPU, 14nm / 16nm manufacturing process has enabled performance and power consumption. The demand balance is very good. The author believes that it is better to solve the physical limit of 7nm relative to a large number of resources.
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