"If you study programmable logic design, you must have been exposed to CPLD and FPGA. What are the differences between them? Just as you see the title, whether to say CPLD or FPGA is not the point. Maybe you can get such an answer. CPLD is based on macro unit and adopts EEPROM technology. It does not need external configuration devices and is switched on instantaneously when powered on; FPGA is based on look-up table structure and adopts SRAM technology. External reconfiguration is required for power on, but there are more logic resources than CPLD; In general, CPLD is suitable for combinational logic design, while FPGA is more suitable for complex sequential logic design. These are not wrong, but with the progress of technology and the improvement of chip integration, the difference between CPLD and FPGA has become more and more blurred.
The advantages of CPLD are outstanding, but the density of logic unit reaches the upper limit due to the structural limitation of macro unit. How to break through the traditional CPLD architecture, Altera has made a revolutionary design as early as its max II series devices. As shown in the figure below, the max II device adopts the same high-density logic unit design as FPGA, and the nonvolatile flash memory block is integrated on the chip as the configuration module, which can not only improve the logic unit density of the chip, but also realize the instantaneous power on capability like CPLD device.
Max II device plan
This year Altera launched its latest Max 10 series (max 10 Data Book) programmable devices, which can be said to be another revolution of CPLD and has completely blurred the boundary between CPLD and FPGA. Max 10 not only inherits the characteristics of the previous max series devices, but also greatly improves the logic resource density, with a maximum of 50K logic unit (LE), which is not inferior to some low-end FPGA devices. More importantly, Max 10 also includes full-featured FPGA features, such as embedded processor soft core, DSP module, DDR3 storage controller and so on. It can be said that Max 10 is actually a nonvolatile FPGA.
Max 10 architecture
You can learn about the new features of Max 10 through the above architecture diagram:
Dual configuration flash memory: two images can be stored on one chip and dynamically switched between images
Analog module: Integrated ADC, power management and temperature sensor
Momentary on: Configuration time in milliseconds
Nios II soft core embedded processor: it supports the integration of Altera soft core Nios II embedded processor and provides a single-chip, fully configurable instantaneous connection processor subsystem.
DSP module: the first nonvolatile FPGA with DSP
DDR3 external memory interface: Max 10 supports DDR3 SDRAM and lpddr2 interfaces through soft core IP storage controller, which is suitable for video, data path and embedded applications.
User flash: it has 736 KB user flash code storage function and supports Nios II embedded applications. The user's flash memory capacity depends on the configuration selection.
At present, Max 10 series has 7 product lines, from 10m02 to 10m50, and logical units from 2000 to 50000, as shown in the figure below.
Max 10 product line
CPLD generally has lower unit cost IO, so it is often used in the design of combinational logic and switch selection. From the above table, it can be seen that the maximum logic resources of Max 10 devices reach 50000 and the user IO also reaches 500. At the same time, Max 10 FPGA is very suitable for cost-effective single-chip scheme, so Max 10 is suitable for many market fields and applications. For example, it can be used as I / O module or video monitoring in industry. Max 10 series provides chips in commercial, industrial and automotive temperature ranges at the same time, so Max 10 can play a great role in industrial, automotive and consumer fields.
Evaluation Kit ek-10m08e144es / P
Of course, the evaluation and design of FPGA circuits must require a development board. At present, four Max 10 development kits have been launched. Aiban has received the max 10 FPGA Evaluation Kit ek-10m08e144es / P from Altera. Let's take a look at this cost-effective entry Evaluation Kit（ (next page)
Max 10 FPGA Evaluation Kit
Altera's max 10 FPGA Evaluation Kit is a low-cost entry kit that currently sells for no more than $50. The evaluation kit adopts a very simple plastic package, a development board and a mini-b USB cable. In particular, the package also comes with plastic pads for four development boards.
Evaluation board, USB cable, plastic foot pad
The structure of the max 10 FPGA Evaluation Kit is very simple. Except for some peripherals such as keys, switches and LEDs, it is a variety of expansion interfaces,
Max 10 FPGA Evaluation Kit block diagram
The evaluation suite leads out 80 gpios for users. In addition, there is the standard interface of Arduino R3, and even a small "prototype area" hole board is reserved. Therefore, the max 10 FPGA evaluation suite is very suitable for tossing. Doing prototype design or DIY learning can be said to be very flexible.
Max 10 FPGA Evaluation Kit front
Max 10 FPGA Evaluation Kit back
The main features of the max 10 Evaluation Kit ek-10m08e144es / P include:
Core device Max 10 FPGA (10m08sae144c8ges, single power supply, 144 pin)
Enpirion EP5388QI （ Ep5388qi Data Book) load point powersoc: 800 Ma, DC-DC step-down conversion, with integrated inductance
10pin JTAG
50 MHz crystal oscillator
Switches, buttons, jumpers and status LEDs
Arduino R3 compatible interface
80pin GPIO extension interface
mini-B USB interface
Reserved potentiometer layout
In addition, it should be noted that the mini-b USB interface of the development board is only used as the power supply interface, and the maximum output current of the DC-DC conversion power chip on the board is 800mA. The development board only provides JTAG programming interface and supports Altera's USB blaster and Ethernet blaster download cables. If you don't have Altera's programming download cables, you need to purchase extra to build the development environment.
Let's take a look at the core FPGA device 10m08sae144c8ges on the development board. From the previous Max 10 product list, we can know that Max 10 is divided into seven product families according to different logic resources and functions. Each product family is divided according to packaging, speed and temperature levels, as shown below:
Max 10 device identification definition
In this way, we can understand some general characteristics of the chip 10m08sae144c8ges on the development board, such as 8000 logic unit, single power supply, 144 pin QFP package, commercial temperature level, speed level 8, engineering sample, etc.
10m08sae144c8ges device QFP package
Main features of 10m08sae144c8ges:
TSMC's 55nm embedded flash process is adopted
144pin QFP package, 22mm x 22mm size, maximum number of user IO 101
8000 logic unit (LE), supporting internal memory module, multiplier, PLL and user flash memory
Internal dual boot self configuring flash, supporting JTAG
Support embedded hard core IP, such as external memory control and 1-way 12 bit ADC
Single power supply, only one 3V or 3.3V power supply is required
To learn more, you can refer to the documentation of the max 10 device. Next, prepare the power on trial evaluation kit（ (next page)
development environment
Those who develop with programmable devices know the importance of EDA tools for FPGA, and it is not a small challenge to be familiar with EDA tools. Max 10 is a new device launched by Altera. The supported Quartus II software version is more than 14.0.2. At present, the latest version is 14.1. There's no way. First, go to Altera's official website to download Quartus II.
Quartus II software download page
Quartus ii14.1 has a large file, including main file, Modelsim file and device support file, which can be downloaded as required. Here's a reminder that versions after Quartus ii14.0 can only run on 64 bit systems.
Max 10 FPGA Evaluation Kit only provides JTAG interface, so to build the development environment, there must be Altera download cable, such as USB blaster,
USB blaster download cable
When installing Quartus II, you will be prompted to install the USB blaster driver, so that the whole development environment is ready.
Power on operation
After the preparations are completed, we'll power on to see the work of Max 10. The preset program on the Evaluation Kit is to light the user led and flash every 0.5s. After connecting the USB, the max 10 is powered on instantaneously. Compared with ordinary FPGA, it takes time to configure the program, which is really much faster. The internal flash configuration time of Max 10 only takes 10ms, which can't be felt at all.
Evaluation suite built-in program
Now you can start your own FPGA design on Max 10. Altera's design store provides a series of routines for the max 10 evaluation suite, which is essential for novices.
Max 10 FPGA Evaluation Kit design store
The project file downloaded in the design store is a packaged. Par file, which can be decompressed in the command line mode. For details, see the instructions on the web page. The Quartus ii14.1 version adds the function of directly importing file templates, which makes the import routine more convenient. Under the file menu, select new project wizard to create a new project,
Import routine
Here you can directly import the project template. For example, we import the baseline design routine. The top file of this program only has pin definitions and does not complete any functions. However, this program is very useful because it has defined the pins of the max 10 chip on the max 10 Evaluation Kit. Any design we start later can be based on this routine, so there is no need to reset the pins. The definition of each pin can be seen in the assignment Editor under assignment, and we can also modify it manually. Of course, you can also see the graphical layout of pins through the pin planner.
Evaluation Kit Max 10 chip pin definition
(next page)
Dual boot flash configuration
The most important change of max series CPLD After Max II is the built-in flash configuration module, so as to realize the instantaneous power on of CPLD. Max 10 introduces an interesting new technology, built-in dual boot mode, which can realize dual configuration in one chip through the boot of the chip_ SEL pin realizes the switching of two configurations.
Configuration diagram
The single chip dual configuration scheme makes your design more flexible and saves cost in some occasions where additional flash chip configuration is required. The max 10 series can support dual start mode except 10m02.
Flash in Max 10 chip can be divided into configuration module (CFM) and user module (UFM). Cfm0 module is specially used for configuration, while cfm1 module can be used as UFM in single configuration mode. For example, the flash size in 10M08 chip is 2496kb, of which cfm0 accounts for 1120kb and cfm1 accounts for 1120kb. In this way, the user's available flash is only 256Kb in dual boot mode, while the user's available flash can reach 1376kb in single configuration mode. The internal configuration of the max 10 chip has five modes:
Dual compressed image (256Kb UFM)
Single compressed image (1376kb UFM)
Storage initialized single compressed image (256Kb UFM)
Single uncompressed image (912kb UFM)
Storage initialized single uncompressed image (256Kb UFM)
The configuration mode can be set in the device and pin option under device in the assignment menu
Set project configuration mode
IP core is becoming more and more indispensable in today's FPGA design. The dual configuration function also needs to use Altera dual configuration IP. The realization of dual configuration needs to be divided into three steps:
Add dual boot IP in project
Configuration mode: select internal dual configuration mode
Convert the sof files of two projects into POF files by using Convert program file
Altera's design store provides a dualboot routine, which is a simple dual boot program when booting_ When sel = 0 (switch 6 in switch SW3) turns on LED1 and LED2 alternately, while boot_ When sel = 1, LED3 and LED4 are turned on alternately. The two project files of dualboot routine are integrated in one project,
Dual_ Boot routine
The routine has instantiated the dual configuration IP - dual in the program_ image_ Boot, open qsys to see the IP connection,
Dual_ boot IP
After compiling image0 and image1, sof files will be generated. Open convert program file under file to convert the final POF file
Generate POF programming files
Finally, you can download the program to the internal flash of Max 10.
Compile Max 10 interface
Power on again after downloading
The sixth switch of SW3 is up, and LED1 and LED2 are lit alternately
The sixth switch of SW3 is down, and LED3 and LED4 are lit alternately
You can see that changing the 6th switch of SW3 can change the configuration program of Max 10. In general, it is also convenient to add dual configuration function,
First, use the qsys tool to generate a dual boot IP. Here, pay attention to the clock frequency and connection;
Then instantiate the IP into our program, you can refer to the routine;
Then modify the configuration mode of the project;
Finally, it is converted into a POF file that can burn flash.
Summary
This paper introduces the latest Max 10 programmable device with nonvolatile performance introduced by Altera, which has the capacity of FPGA
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