Cadence helps creative electronic 20 nanometer SOC test chip

Global Electronic Design Innovation Leading Enterprise Cadence Design System Company Recently announced that Design Services Creative Electronics (GUC) uses Cadence® Encounter® Digital Implementation System (EDI) and Cadence LED Physical Analyzer successfully completed 20 nano-system level chip (SOC) test Chip flow. Both engineers use Cadence solution to overcome the implementation and manufacturability design (DFM) verification challenge by close cooperation, and finally complete the design. In the development process, creative electronics uses Cadence Encounter solutions to support all complex steps of 20 nano-layout wiring processes, including dual graphic library preparation, layout, clock tree integration, fixed, wiring, and wiring. Creative companies also use Cadence Litho Physical Analyzer for DFM authentication, turn the uncertainty of 20 nano-process variations into a foreseeable impact to help shorten the design cycle. "We choose Cadence as this development partner because Cadence has confirmed experience in advanced nodes," Mr. Zeng Kewen, Director of Creative Electronic Design Method, said. "TSMC 20 Nano SOC Test Chip's Success Flow is the direct results of both parties and high performance performance of Cadence Encounter and DFM solutions." "As customers turn to 20 nanometers, they are facing new challenges, such as double-shaped and process variations, etc.," Dr. Xu Jiping, senior Vice President of Cadence Silicon Realization Group. "Cadence has resolved the challenges of these advanced nodes in implementation and DFM verification tools. Companies are working closely with partners to verify these new processes to reduce risks, making it easier to make customer chests to turn into 20 nano-process nodes.

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