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    Cypress launches the world's most flexible single-chip ARM Cortex-M0 solution

     

    Cypress Semiconductor has launched a new series of PSoC 4 programmable on-system architecture. The new PSoC 4 L series is the most integrated single-chip solution with 32-bit ARM Cortex-M0 kernel, 256KB flash, 98 general I / O, 33 programmable simulation and digital modules, 1 USB device control And 1 Control LAN (CAN) interface. The PSoC 4 L series solves the product change problem by means of the PSoC architecture, using Cypus industry-leading Capsense capacitive touch induction technology to achieve a reliable and beautiful user interface, so it is an ideal solution for various industrial and consumption applications. . John Weil, Vice President of Cypress MCU Marketing, said: "Award-winning PSOC 4 product line allows customers to easily migrate from their proprietary 8-bit and 16-bit MCUs to the highest integration ARM Cortex-M0 system. PSoC 4 L series introduces new features, such as the highest 94 channel dual-mutual capacitance required for home appliances of large capacitive touch interfaces; USB and Bit-Perfect) Digital Audio Solutions Develop USB and Programmable digital module. In addition, the series also has all resources needed to create new USB Type-C products. " The PSoC 4 L Series is equipped with 13 programmable analog modules, including 4 high performance operational amplifiers, 4 current output digital-to-analog converters (IDACs), 2 low power comparators, 1 12-bit SAR ADC and the highest A dual Capsense module for 94 capacitive sensing channels is supported. The programmable analog module allows the engineer to customize the front end of the developer to achieve new features of the terminal product, do not increase the cost, size and power consumption of the product. The PSoC 4 L Series is equipped with up to 20 programmable digital modules, including 8 timer / counter / PWM modules, 4 serial communication modules, and 8 universal digital modules (UDBs). The programmable digital module each includes two programmable logic devices, 1 programmable data channel, and status, and control registers. The UDB can be configured as a coprocessor for sharing a computational intensive task of the ARM Cortex-M0 kernel. These modules can also enable engineers to achieve various custom digital peripherals, state machines or glued logic, and traditional MCUs usually require additional ICs to implement them. The extendable PSoC 4 architecture is an easy-to-use PSoC Creator integration development environment (IDE) and PSoC components. PSoC Creator enables parallel design of hardware and firmware to simplify system design, speeding up product listing; PSoC components are free embedded ICs represented in IDE. They can accelerate the final application of prototype design speed while minimizing common PCB modifications and firmware changes. Supply The PSoC 4L series is now available, and it is expected to be mass production in the first quarter of 2016. This series of products will be provided by Cypress and its authorized distributors with 48-pin TQFP, 64-pin TQFP, 68-pin QFN, and 124-pin VFBGA packages. WeChat public account search "Love Board Network" plus attention, daily update development board, intelligent hardware, open source hardware, activities, etc., you can make you full. Recommended attention! [WeChat scanning picture can be directly paid] Recommended based on ARM development board: A MCIMX6SX demo board is based on ARM Cortex-A9 for creating interconnected home and vehicles in an IoT application. NIMBLE7 embedded touch screen computer A custom Android 2.2 development board based on Cortex-A8 can run a network update system. EFM32GG Development Kit A Advanced Energy Saving Application Test Scheme of an ARM Cortex-M3 EFM32TM Giant Gecko Microcontroller. Xiaobian vomiting blood recommendation: FPGA entry must read, the preloader and U-boot of the Cyclone V SoC device are generated FPGA Collaborative Design Collaboration, how to write and run bare metal C procedures for Altera SoCs in ARM DS-5 tools It is not difficult to have a video, teach you how to optimize Memory mapping interconnection with QSYS system tools. Altera expert video explanation, easy to implement transceiver design with QSYS and transceiver toolkits in Quartus II software The most classic teaching video in history, implementing the design of SDI II IP core in Altera Arria 10 devices Altera official video explanation, how to generate Arria 10 instance design using Quartus 14.1

     

     

     

     

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