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    DAC34H84 HD2 Performance Optimization and PCB Layout Suggestions

     

    1 Introduction DAC34H84 is a four-channel, 16 bits, sample 1.25GSPS, a high-performance digital-to-analog converter that is 1.4W high-performance by Texas Instruments (TI). Supports 625MSPS data rate, which can be used for the base station transceiver for broadband and multi-channel systems. Due to the high-speed development of wireless communication technology and the requirements of various types of system of radiofrequency unit (RRU / RRH), the transmitted signal spectrum supported by the radio frequency trapping unit (RRU / RRH) is getting wider and wider, and the intermediate frequency frequencies are generally not The corresponding improvement is improved, so the second harmonic (HD2) of the intermediate frequency transmit DAC issues an intermediate frequency (IF) signal (HD2) or the signal (FS-2 * IF) generated by the intermediate frequency and sampling frequency fs is getting closer to the main signal, so these Nonlinear dispersions are increasingly difficult to filter out of external analog filters. These stray signals reduce the SFDR performance of the transmitter, and optimize the second harmonic performance of the DAC output is becoming more important. 2. Production of secondary harmonics In the ideal state, when the output state of the DAC changes, it should be directly hopped from the current value to the desired new value. However, actually when the DAC output status changes, as shown in the following figure, it is possible to cause overshoot and downstrap. Be Figure 1 DAC output status switching This phenomenon is caused by the interconnection effect of the DAC internal current source adjacent the trace and the state change. The mutual capacity will introduce the current of adjacent lines on the current source line to form crosstalk to form an overshoot or a lower pulse. Be Figure 2 Three Bit Binary DAC As shown in the figure above, the BINARY DAC is used as an example. When the code 011 to 100 state is switched, it is necessary to simultaneously switch three current source switches, which may generate the above overshoot and lowering phenomenon. Be Figure 3 Effect of pulse on sinusoidal signal These overshoot and the lower impulse will produce harmonics of the DAC output signal. Taking the production of sinusoidal secondary harmonics as an example, as DAC shown in the above figure, the number of pulse signals caused by the overshoot and the downframe effect is exactly twice in one cycle, resulting in this sinusoidal signal. Second harmonics. There are two ways to improve DAC secondary harmonic performance: 1. Optimize the reasonable PCB layout of the DAC simulation output. 2. Use a digital predistortion algorithm to produce a signal of the same amplitude, phase phase difference 180 degrees to cancel the harmonics of the DAC. This paper mainly introduces the first method. The DAC's HD2 performance can be optimized by a good PCB line layout. The current RRU transceiver is used by the DAC + IQ modulator solution. The PCB layout between the DAC's analog output port and the IQ modulator's analog input port will directly affect the linearity of the system. If you have a good PCB line layout, the harmonic performance of the DAC + IQ modulator will increase relatively separate DACs. PCB layout typically uses a plurality of consecutive U-shaped winding methods in order to meet equal long line requirements. These U-shaped Multi-frequency are interacting in high tunnel. In addition, the location of the analog output port resistors of the DAC and the IQ modulator affects the continuity of impedance, causing echo. The above two effects will affect the harmonic performance of the DAC. The 2 impact response model of the DAC is as follows: H (t) = a + b * x (t) + C * X2 (T) Assume that the signal is X (t) = k * cos (ωt) through the signal of the DAC I + So h (t) = a + bk * cos (ωt) + CK * COS2 (ωt) = A + bk * cos (ωt) + CK * [COS (2ωt) +1] / 2 = A + 0.5 * CK + BK * COS (ωt) + 0.5 * CK * COS (2ωt) 2 harmonics can be expressed as 0.5 * CK * COS (2 ωt) 2 harmonic echo is DK * COS (2 ωt + φ) = DK * [COS (2ωt) cosφ - sin (2ωt) sinφ] Total 2 harmonic expression is K (0.5 * C + D * cosφ) COS (2 ωt) - DK * SIN (2ωt) sinφ The C, K and ω of all channels of the multi-channel DAC are the same, and the echo-amplitude D and the echo phase φ caused by the PCB layout impedance discontinuity and the mutual inductance effect. They bring the difference in HD2 performance. , Reading the full text, the technology area An interference sharing that can generate two code conversion error zones Circuit design to quarantine on digital ground and simulated ground isolation Electrostatic energy can cause great harm to electronic components such as terminals Basic problem with switching power supply design Combined circuit characteristics combination logic circuit structure

     

     

     

     

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