Due to the limitation of wireless transmission bandwidth, the high-resolution video image obtained by the drone on the ground target reconnaissance must be efficiently compressed to the ground receiving processing system in real time. Existing video compression standards H.261, H. 262, H. 263 and MPEG-1, MPEG-2, MPEG-4 and the like.
Wherein the MPEG-4 due to the compression coding method using an object-based, compared to frame-based compression coding method, temporal and spatial redundancy of each standard conventional lower, while maintaining the decoding quality improving compression ratio. MPEG-4 interaction also have better performance and greater error resilience, as compared to the conventional compression standards, more suitable for radio channel transmission.
More complex video compression algorithms, combined with the UAV payload weight and volume restrictions, it is difficult to achieve real-time video compression encoding airborne images, usually only a low resolution image compression in real time. This article is designed and implemented on-board real-time image compression coding and processing system based on TI's latest media processor TMS320DM642, to achieve the highest resolution D1 video resolution airborne image resolution and compression ratio adjustable MPEG- 4 real-time compression and a constant output process stream.
1 design requirements
Compression processing system to complete the entire airborne PA L of the high-resolution camera output format analog video signal in real time acquisition, compression and transmission.
To facilitate ground receiving and processing real-time analysis of the additional information and the compressed image data of an image, the UAV shall time and spatial location of the captured image other package in real time. MPEG-4 is unequal compression encoding, for convenience of wireless transmission, MPEG-4 stream of data packets need to be compiled frame is formed 256 KB / s constant bit stream of the baseband, for real-time transmission to the wireless channels modulated transmission subsystem. The system needs to dynamically change the resolution of the image and the compression ratio in accordance with the control command.
2 system hardware design
2. 1 TMS320DM642 chip features
DM642 belong to the TMS320C64x DSPs. Veloci T I structure allows C6000 DSPs are widely used in video and image processing.
CPU VLIW architecture by operating in parallel a plurality of execution units, these units perform multiple instructions in a single cycle. Parallel C6000 is the key to achieving high performance. C64x has some important improvements on the basis of C6000. In addition to higher frequency of the external clock, the C64x extended to the structure from the previous VelociTI Veloci TI. 2 structure contains many new instructions, adds additional data channels, the number of registers is also doubled. These extensions so that the CPU can process more data per clock cycle in one operation resulting in higher performance.
DM642 chip integrates a variety of peripherals within the chip, so that the field of image and video application development is more convenient. It can be configured with three video ports, providing video input, video output stream, and seamless interface input.
The video port supports many formats of video input / output. DM642 developed using a video encoder, the video input section needs only to a video capture chip, such as company A DV7181 AD, no external logic control circuit and the FIFO buffer, to make the system more simple and reliable hardware.
DM642 seamless integration of the 64-bit external memory interface (EMIF), synchronous and asynchronous memory enables seamless connection or an external peripheral.
Other peripherals include DM642: 10 Mbps / 100 Mbps Ethernet port (EMAC), multi-channel audio serial interface (McASP), a host interface (HPI), multi-channel buffered serial port (the McBSP) and PCI interface.
2.2 System hardware components
Airborne real-time image compression and processing system TMS320DM642 high-performance general-purpose DSP chip as the core, by the video capture input module, an image compression processing module, the external memory module and transmission control interface module. The hardware system block diagram shown in Figure 1.
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System hardware block diagram of FIG. 1 processing the video image in real-time airborne Compression
Image acquisition module input analog video signal synchronization acquisition, acquisition and decoding video. Data format video output from the decoder as YUV4: 2: 2. Video data decoding the data transmitted to the DMA channel unit via DM642 VPORT channel buffer, to generate an interrupt when a DMA data has been collected. After the image compression processing module, real-time video decoding compressed data according to the received mathematical control command to the cache memory module. Memory modules 32 MB 64-bit SDRAM, to achieve the storage of programs and data.
Transmission control interface module to be cached in the SDRAM at a constant rate transport stream 256 KB / s 8-bit parallel output port to transmit and receive terrestrial transmission control command. The module consists of a FIFO chip and the CPLD, transmits an interrupt signal to DSP FIFO is half-empty. , Reading the full text, the technology area
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