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Image acquisition is an important step in real-time image processing. Currently, the image sensing device mainly has CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide SchiConductor). CCD technology is now very mature, and the CCD camera is still the preferred device for high-end applications. It outputs the analog video signals including image signals, rows and field blanking signals, rows and field synchronization signals. The traditional video acquisition system consists of a A / D conversion circuit, a control logic circuit, a data cache circuit, an address generator, an address decoding circuit, and the like. Such design has a complicated circuit complicated, a wide chip, long development cycle, and cost-effective.
This paper uses a video decoding chip with a complex programmable logic device CPLD (Complex Programmable Logic Device) to overcome the above disadvantages. The video decoding chip can automatically obtain line, field synchronization signals from the video signal, and complete A / D conversion, and the CPLD with the system programming (ISP) function can be logically reconstructed by software, and logic control, address generator All circuits are integrated into a piece of chip. The system has the advantages of small size, low cost, high reliability, easy upgrade, and short development cycle.
1 Video decoding chip SAA7114H performance characteristics
SAA7114H is a highly integrated circuit that has a wide range of applications in the video capture. Video decoding is based on row lock clock decoding principles, which can convert PalseCAM and NTSC system signals to standard video signals compatible with ITU 601 standards. The SAA7114H is capable of receiving the TV CVBS signal or VCR of the TVR, while also capable of receiving the digital video signal of the MEPG code stream or VIDEO Phone stream through its extended interface (X port). After the SAA7114H, the video signal is decoded, and the data output format of 8-bit or 16-bit width can be selected according to the actual application.
The main task of SAA7114H is to capture and zoom video images, providing a standard YUV digital video stream output format to the display controller. The main features of SAA7114H are as follows:
(1) Programmable static gain or automatic gain control can be selected for each CVBS or Y / C input signal.
(2) Contains two 9-bit video A / D converters, which can receive the input of the digital CVBS signal or Y / C signal in the extended interface.
(3) Digital phase locked loop is suitable for synchronous processing and clock generation of various standards and non-standard video signal sources.
(4) Detection of horizontal and vertical synchronous signals.
(5) Indicate the line locking clock in accordance with the ITU 601 standard.
The SAA7114H also provides an I2C interface, which is connected to the master chip, so that the internal registers can be read and write, control the working state of SAA7114H.
After the SAA7114H, the video signal is decoded, and the correct timing correspondence must be kept correctly, and the original video image can be completely indefinished. The timing of the SAA7114H output includes a line of synchronization signals, row yard signals, row frequency field frequency, field identification signals, and the like. Taking the PAL system as an example, its row, the field timing relationship is shown in Figure 1.
Among them, the HREF signal is a row blanking signal, and Vgate represents a field blanking signal (which can be determined by programming the register VSTO [8: 0] and VSTA [8: 0]), HREF and V123 signal combination can determine the current The field or even the game, the FID is a field identification signal. The above signals can be output through the relevant pins of SAA7114H (eg RTSO, RTSI, XRH, and XRV pins, etc.).
2 Complex programmable logic device XC95216 performance characteristics [2]
XC95216 is a complex programmable logic device of Xilinx, with rich programmable I / O pins, features and flexible features. Not only can conventional logic features, but also complex timing logic functions. Its main features are as follows: up to 166 users I / 0 pins, all pin foot logic delayed 10ns, Fcni can reach 111MHz, 216 macro units, with 4,800 available doors.
3 real-time image acquisition system composition and its working principle
The real-time image acquisition system designed herein is an image acquisition section of a DSP-based active target tracking system. DSP performs related calculation processing, identifying the target, and then controls the purpose of tracking targets for the digital image signal provided by the image acquisition portion. The system requires strong real-time, small size.
The video decoding chip SAA7114H is designed to convert the analog video signal obtained by the CCD camera into a digital signal. In this real-time image processing system, the constant video decoding chip SAA7114h needs to be added to the buffer circuit between the transmission DSP image processing. The buffer circuit generally has three structures: double-port RAM structure, FIF0 structure, ping-pong cache structure. The first two buffers have a relatively small storage capacity, not particularly suitable for high-speed image processing systems. The characteristics of the ping-pong cache structure determine that the peripheral logic devices can be composed of double-port RAM and high speed FIFO more suitable for buffer memory required for video processing systems than double-port RAM and high speed FIFO. The CPLD is used to control two SRAMs to work in ping-pong, and implement high-speed transmission of data streams in the system.
3.1 Workflow for video capture
The hardware block diagram of the video capture is shown in Figure 2. After the system is reset, the MCU (MCU) initializes Saa7114H through the I2C bus. The single chip features P89C61X2BN's P89C61X2BN in Philips, allows to change the SAA7114H initializer, and can be bonded to the single-chip flash, which is quite convenient. After the initialization is successful, SAA7114H starts working, converts the input analog video signal to 720 × 576 YUV422 digital signal, then enter the CPLD. CPLD on one aspect of format conversion, output YUV4: 1: 1, CIF. The format digital signal, on the other hand, as an address generator, input to the SRAM with the CIF, format data. The CPLD also generates SRAM read and write control signals, using two SRAMs, working in ping-pong, and saves an image per piece. Figure 2 is directed to DA [7: 0] ports to DB [7: 0], indicating DB [7: 0] ports, indicating DA and DB ports. After the image is saved, the CPLD notifies the DSP in an interrupt method for the corresponding processing.
3.2 Ping Pong Cache Control Principle
"Ping Pong Operation" is a process technology that is often applied to data stream control. A typical ping-pong operation method is shown in Figure 3. The processing flow of the ping-pong operation is as follows: The input data stream is passed through the "Input Data Selection Unit" (in this acquisition system, the internal logic structure of the CPLD completes this data selection function), and the data stream is assigned to the data buffer SRAM A and SRAM. B. In the first time, the input data stream is cached to SRAM A. In the second time, through the switching of the "input data selection unit", the input data stream is cached to SRAM B, and the data of SRAM A (first image data), output data selection unit "The selection is sent to the" Data Flow Calculation Module "(DSP) operation. In the third buffer cycle, the input data stream is cached to SRAM A by "input data selection unit", while the data (second image data) of SRAM B (second image data) is outputted by "output data selection unit) "Switch, sent to" Data Stream Calculation Module "operation processing. This is cycled, and the week is beginning.
The maximum feature of ping pong operation is to switch to the "data stream operation module" to "data stream operation module" by "input data selection unit" and "output data selection unit", in combination, mutual switching, will be sent to the "Data Flow Calculation Module" for operation And treatment. Take the ping pong operation module as a whole, the input data streams at both ends of this module are continuous, without any pause, so it is very suitable for pipeline processing, complete data seamless buffering and processing.
3.3 CPLD design
3.3.1 Data Cache
Save data to SRAM, you need to generate an address while sampling. There are two groups of address lines per SRAM, and a set is given by CPLD, and a set is given by DSP. In order to solve the resource conflict in the shared memory, the disconnection between DSP and SRAM, CPLD, and SRAM needs to be controlled [3]. The CPLD passes the address line, data cable, and chip select signals of the CPLD to SRAM B when the CPLD is operated by providing the bus isolator, and sets the isolator to turn the DSP to SRAM B. Disconnected from SRAM A, at which time the DSP can read SRAM B, and vice versa. In fact, the SRAM's data lines also have two groups, the same work mode, and address line. In order to read the data in the RAM to the DSP, it is also necessary to control different RAMs different from each image to make two SRAMs work in ping-pong. ISSI company IS61LV5128 is selected in the design with a capacity of 512KB.
3.3.2 interface
The main peripheral interface of the CPLD is as follows: (1) Input section. Image data LPD [7: 0], clock LCLK, field synchronization VREF, row synchronization HREF, reset RES. (2) Output section. Image Data IP01 [7: 0] and IP02 [7: O], chip selection signal EEL, CE2, write enable Wel, WE2, address addl [18: 0], ADD2 [18: O], bus isolator switch Signals F1, F2, DSP interrupt signal DSPINT (0E signals for setting SRAM here, because the CPLD only needs to write data to SRAM, and does not need to be read from the SRAM).
3.3.3 VHDL implementation
The CPLD is logically implemented in the design. The "Ping Pong" control part of the program is as follows:
This article designs a real-time image acquisition system based on video decoding chip SAA7114H and CPLD, its hardware structure is simple, system stable, fully meet the needs of DSP-based active target tracking system, has strong practicality, slightly change In other occasions, such as monitoring systems, etc.
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