"The work of the analog circuit relies on continuous changes. The work of digital circuitry depends on the receiving end according to the predefined voltage level or threshold for high level or low level, it is equivalent to the" true "true" "Or" false ". There is a" gray "area between the high level and low level of the digital circuit, and the digital circuit in this area sometimes exhibits analog effect, for example, when a high level (state) is jumped from a low level (state) When it is changed, if the speed of the digital signal is fast enough, the overshoot and ringback reflective phenomenon will be generated.
For modern plate design, the concept of mixed signal PCB is relatively blurred because there is still analog circuit and simulation effect even in a pure "digital" device. Therefore, in the initial design of the design, the simulation effect must be simulated in order to reliably realize strict timing allocation. In fact, in addition to the communication product must have the reliability of the failure for several years, a large number of low-cost / high-performance consumer products in production requires simulation of simulation effects.
Another difficulty in modern mixed signals PCB design is that there are more and more devices of different digital logic, such as GTL, LVTTL, LVCMOS, LVDS logic, the logic threshold and voltage swing of each logic circuit, but these different logic thresholds The circuitry of the voltage swing must be designed on a PCB. Here, by thoroughly analyzing the layout and wiring design of high density, high performance, mixed signal PCB, you can master success strategies and techniques.
First, mixed signal circuit wiring foundation
When the numbers and analog circuits share the same components on the same board, the layout and wiring of the circuit must pay attention to the method. The matrix shown in Figure 1 helps the design plan of the mixed signal PCB. Only the characteristics of the digital and analog circuits can be reached in the actual layout and wiring to achieve the required PCB design goals.
Simulation and digital circuit: two aspects of mixed signal design
In the mixed signal PCB design, there is a special requirement for the power trace and require analog noise and digital circuit noise to avoid noise coupling, so that the complexity of layout and wiring increases. The special demand for the power transmission line and the requirements of noise coupling between the analog and digital circuits, the complexity of the layout and wiring of the mixed signal PCB is further increased.
If you connect the power supply of the A / D converter and the digital power supply of the A / D converter, it is likely to cause the mutual influence of the analog portion and the digital partial circuit. Perhaps, due to the input / output connector position, the layout scheme must mix the wirings of the numbers and analog circuitry together.
Before the layout and wiring, engineers should figure out the basic weaknesses of layout and wiring schemes. Even if there is false judgment, most of the engineers tend to use layout and wiring information to identify potential electrical impacts.
Second, the layout and wiring of modern mixed signals PCB
The following will be described below with the design of the OC48 interface card to describe the technique of the mixed signal PCB layout and wiring. The OC48 represents the optical carrier standard 48, which is basically a 2.5GB serial optical communication, which is a kind of high-capacity optical communication standard in modern communication equipment. The OC48 interface card contains a number of typical mixed signal PCB layouts and wiring issues, and its layout and wiring process will indicate the order and steps of solving mixed signal PCB layout schemes.
The OC48 card contains an optical transceiver that implements both optical signals and two-way conversion of analog electrical signals. Analog signal input or output digital signal processor, DSP converts these analog signals into digital logic levels, can be connected to microprocessors, programmable gate arrays, and system interface circuits for DSP and microprocessors on OC48 cards. . Independent phase locked loops, power filter and local reference voltage sources are also integrated.
Among them, the microprocessor is a multi-power device, the main power supply is 2V, 3.3V I / O signal power supply is shared by other digital devices on the board. The independent digital clock source is OC48 I / O, microprocessor and system I / O provide clocks.
After examination of the layout and wiring requirements of different functional circuit blocks, 12-layer plate is recommended, as shown in Figure 3. The configuration of the microstrip and strip lines can safely reduce the coupling of adjacent traces and improve impedance control. A ground layer is provided between the first layer and the second layer, and the wiring of the sensitive analog reference source, the CPU core, and the PLL filter power source will be isolated from the microprocessor and the DSP device of the first layer. The power supply and the ground plane are always pairs, and the OC48 card is the same as the shared 3.3V power layer. This will reduce the impedance between the power and the ground, thereby reducing the noise on the power signal.
To avoid digital clock and high frequency analog signal lines adjacent to the power layer, the noise of the power signal will be coupled to the sensitive analog signal.
To carefully consider the opening (split) of the mounting ground plane according to the needs of the digital signal wiring, especially in the input and output of the mixed signal device. The adjacent signal layer passes through a opening trace causes the impedance discontinuous and poor transmission line. These will cause signal quality, timing and EMI issues.
Sometimes a number of ground layers is added, or a sever-locally used a local power layer or a ground layer is used under one device, and the opening and avoiding the above problems are canceled. A plurality of ground layers are used on the OC48 interface card. Keep the stack symmetry of the position of the opening layer and the wiring layer to avoid the card deformation and simplify the production process. Since the 1 ounces of copper-resistant resistance, the 3.3V power layer and the corresponding ground layer should be used in 1 ounce copper plate, other layers can be used in 0.5 ounce copper, which can reduce transient high current or spikes. Voltage fluctuations.
If you design a complex system from the ground floor, a card with 0.093 inches and 0.100 inch thickness should be used to support the wiring layer and the ground isolation layer. The thickness of the card must also be adjusted according to the wiring characteristic size of the via pads and the holes to make the drilling diameter and the width ratio of the finished card thickness do not exceed the aspect ratio of the metallized hole provided by the manufacturer.
If you want to design a low-cost, high-yield commercial product with the minimum number of wiring layers, you should carefully consider all special power supplies on the mixed signal PCB before layout or wiring. Before starting the layout and wiring, let the target manufacturer review the initial layering solution. Basically, according to the thickness of the finished product, the weight of the layer, copper, impedance (with tolerance) and the smallest via pads and holes are hierarchically, and the manufacturer should provide layered recommendations in writing.
It is recommended to include all controlled impedance strip lines and microstrip lines. To combine your prediction with the prediction of impedance, the combination of impedance is considered, and then these impedance predictions can be verified that signal wiring characteristics in the simulation tool for developing CAD wiring rules.
Third, OC48 card layout
The high-speed analog signal between the optical transceiver and the DSP is very sensitive to external noise. Also, all special power supplies and reference voltage circuits also generate a large amount of coupling between the analog and digital power transmission circuits. Sometimes, the shaped limit of the housing has to design a high-density board. Since the orientation of the external fiber optic cable access card is higher than the size of the optical transceiver part, the position of the transceiver is largely fixed. System I / O connector position and signal allocation are also fixed. This is the basic work that must be completed before the layout.
Like most successful high-density simulation layouts and wiring schemes, the layout must meet the requirements of the wiring, the requirements of layout and wiring must be taken into account. The local CPU kernel of the simulation section and 2V operating voltage of a mixed signal PCB is not recommended to use "first layout wiring". For OC48 cards, the DSP analog circuit part contains a portion of the analog reference voltage and analog power supply bypass capacitance to interact. After completing the wiring, the entire DSP with analog components and wirings is to be placed nearly close to the optical transceiver, and sufficiently ensures that the high-speed simulated differential signal to the DSP is the shortest, and the bending and theft are least. The symmetry of differential layout and wiring will reduce the impact of common mode noise. However, it is difficult to predict the best solution for the layout before the wiring.
To consult the chip distributor to consult the design guide of PCB board. Before designing the guide design, you should fully exchange with the distributor's application engineer. Many chip distributors have strict time limits for providing high quality buckle proposals. Sometimes they provide a solution to the "first-level customer" that uses the device. In the field of signal integrity (Si) design, the signal integrity design of new devices is particularly important. Based on the basic guidelines of the distributor and combined with each power supply and the specific requirements of the ground pin, the OC48 pickup of the DSP and the microprocessor can be started.
After the position and wiring of the high frequency simulation portion, the remaining digital circuitry can be placed in accordance with the packet method shown in the block diagram. Be careful not to design the following circuit: the position of the PLL power filter circuit in the CPU of the analog signal sensitivity; the local CPU kernel voltage regulator; the reference voltage circuit for the "Digital" microprocessor.
Electrical and manufacturing criteria for digital wiring can only be applied to the design. The aforementioned design of signal integrity of high-speed digital bus and clock signal reveals some special wiring topology requirements for the delay in the processor bus, balance TS and some clock signal wiring. But you may not know, and some people have proposed recommendations, that is, increase the number of end-connected resistors.
In the process of solving the problem, it is of course a matter of course. However, prior to starting the wiring, one step is to verify the timing of the digital part according to the layout scheme. At this moment, the full DFM / DFT layout review of the board will help ensure that the card meets the needs of our customers.
Fourth, OC48 card digital wiring
For the digital part of the digital device power cord and the mixed signal DSP, the digital wiring begins with the SMD outline map (escape pattern). To use the shortest and widest print lines allowed by the assembly process. For high frequency devices, the printer of the power supply is equivalent to a small inductor, which will deteriorate the power supply noise, causing undesired coupling between the analog and digital circuits. The longer the power supply line, the greater the inductance.
The use of digital bypass capacitors can be optimally layout and wiring schemes. Briefly, the location of the bypass capacitor is fine-tuned as needed, so that it is convenient and distributed around the number of digital components and mixed signal devices. To use the same "shortest and broader trace" method to wiring the bypass capacitor outline map.
When the power branch is to pass through a continuous plane (such as the 3.3V power layer on the OC48 interface card), the power pins and the bypass capacitor do not have to share the same outlet map, you can get the lowest inductance and ESR bypass. On the mixed signal PCB of the OC48 interface card, pay special attention to the wiring of the power supply branch. Remember, additional bypass capacitors are placed in the form of matrices on the entire card, even if they are also placed in the vicinity of passive devices.
After the power outage is determined, you can start the automatic wiring. The ATE test contact on the OC48 card is defined at logic design. Be sure that ATE comes into contact with 100% node. In order to achieve ATE test in order to achieve a minimum ATE test probe in 0.070 inches, the position of the Breakout VIA must be retained to ensure that the power layer will not be partitioned by the via the antipads.
If a power supply and the ground layer opening (SPLIT) scheme should be used, a Layer Bias should be selected on the neighboring wiring layer parallel to the opening. The wiring area is prohibited in the adjacent layer according to the circumference of the opening area to prevent the wiring from entering. If the wiring must pass through the open area to another, it should ensure that another layer adjacent to the wiring is a continuous ground layer. This will reduce the reflection path. Let the bypass capacitor across the open-open power layer is good for some digital signals, but it is not recommended to bridge between numbers and analog power layers because noise will be coupled to each other by bypass capacitance.
Several latest automatic wiring applications can wiring high-density multi-layer digital circuits. In the preliminary wiring stage, the package type of 0.050 inches should be used in the SMD outlet and consider the package type used, and the follow-up phase should allow the position of the via to be close to each other, so all tools can achieve the highest bar gear rate. And the lowest overhead number. Since the OC48 processor bus uses an improved star topology, its priority is highest during automatic wiring.
Summarize
Signal integrity check and timing simulation after the OC48 card board is completed. Simulation proves wiring guidance to achieve the expected requirements and improve the timing indicators of the second layer bus. Finally, design rules check, final manufacturing review, lazer, and check and issue it to the manufacturer, then the floor mission is officially ended. "
Our other product:
