"This paper presents a design method of real-time image acquisition and processing system. The system takes TMS320DM642 [1-2] as the core, combined with video decoding chip saa7115h and OSD FPGA to form the circuit of real-time image acquisition and processing system.
1. Overall system design
1.1 system structure
The system takes TMS320DM642 as the core and adopts the modular design idea. The whole system is mainly composed of video decoding chip (A / D conversion chip), programmable logic gate array (OSD FPGA), TMS320DM642 and peripheral circuits. Peripheral circuits mainly include CCD camera, SDRAM image memory, flash program memory and TMS320DM642 peripheral circuits (reset, power connection, etc.). Figure 1 is the structural block diagram of the system.
1.2 system working principle
The PAL image captured by the CCD camera is transmitted to the SAA7115 decoder. The SAA7115 decoder converts the signal into a parallel BT.656 image code stream and sends it to the TMS320DM642 video port VP0. The TMS320DM642 decodes it again to obtain the image in YUV (4:2:2) format, and transmits it to the dynamic memory (SDRAM) for storage through EDMA. The image size is 720 & times per field; 288 (W & tines; High), 720 & times per frame; 576 (W & ties; High). The CPU accesses the image data in the SDRAM and performs corresponding image processing according to the corresponding program.
In the real-time image processing system, in order not to affect the data processing speed, a buffer circuit needs to be added between the constant speed CCD image acquisition and the variable speed TMS320DM642 image processing. The buffer adopts the ping-pong buffer structure of on-chip FIFO and off-chip SDRAM of TMS320DM642 video port“ "Ping pong operation" is a processing method often applied to data flow control, as shown in Fig. 2. Its processing flow is as follows: the input data flow allocates the data flow to data buffers 1, 2 and 3 through the pointer, and caches the input data flow to 1 at the time of frame 1; In the second frame, the input data stream is cached to 2, and at the same time, the data of 1 is processed. In the next buffer cycle, switch again to cache the input data stream to 3, and at the same time, process the data operation of 2. In this cycle, a, B, C, D and E are five states.
The biggest feature of Ping Pong operation is to switch according to the beat and cooperate with each other, and calculate and process the buffered data stream without stopping. The ping pong operation module is regarded as a whole. The input data stream and output data stream at both ends of this module are continuous without any pause. Therefore, it is very suitable for pipeline processing to complete the seamless buffering and processing of data.
2 function module design
2.1 video acquisition module
The system uses the SAA7115 video decoding chip of Philips company to digitize the CCD analog video, and then transmit it to the video port of TMS320DM642 for processing. At the same time, the horizontal synchronization (xrh) and vertical synchronization (xrv) signals are separated.
The video decoding chip adopts SAA7115, which saves the design of clock synchronization circuit, simplifies the interface circuit and improves the reliability of the system. The analog signal collected by the camera enters the analog terminal al11 of the decoder SAA7115 through the video terminal. After analog processing and a / D conversion, the digital chroma signal and brightness signal are generated and processed respectively. The result of luminance signal processing is sent to the signal processor for comprehensive processing to generate y and UV signals. After formatting, it is output from IPD [7-0] in 4:2:2 YUV format and directly connected to VP0 [9-2] pin of TMS320DM642 video port; The other circuit passes through the synchronization separator, and the corresponding synchronization signal is generated by the digital PLL, which is connected with vp0ctl0 and vp0ctl1 of TMS320DM642. At the same time, the PLL drives the clock generator to generate a 27 MHz clock synchronization signal LLC, which is output to the vp0clk0 pin of TMS320DM642. The principle of video interface between decoder SAA7115 and TMS320DM642 is shown in Fig. 3.
All these functions are completed under the control of I2C bus. SCL is connected with SCL of TMS320DM642 as the clock line of I2C interface, and SDA is connected with SDA of TMS320DM642 as the data address line of I2C interface. Through the timing coordination of SCL and SDA, data can be written or read out from the register of SAA7115 by TMS320DM642.
2.2 TMS320DM642 image processing module
In this system, the video port VP0 is used as the input and connected with the IPD of the video decoder SAA7115. After the BT.656 data stream from the decoder SAA7115 enters the VP0 port, it enters the video port buffer through the BT.656 capture channel. Each video port has a video input / output buffer of 5120 B. the data input from the video port enters the capture FIFO A and FIFO B respectively, in which the Y cache 2560 B, CB and Cr cache 1280 B respectively. According to the output synchronization pulse, control signals such as address signal, read-write and chip selection of frame memory are generated, the image is stored in SDRAM memory frame by frame, and TMS320DM642 is notified to read through interrupt. TMS320DM642 realizes data transfer between video port buffer and on-chip L2 memory through EDMA events. The user sets a buffer threshold to generate EDMA events. The data in BT.656 format flows through the capture channel into their respective buffers and is packaged into 64 B double words. When the double word increases to the buffer threshold, the EDMA event is triggered, and the memory mapping register is used as the source address of EDMA data transmission. In order to ensure that all data of each field can be transmitted without omission, the data size transmitted by EDMA each time shall be equal to the threshold. Due to the powerful processing ability of TMS320DM642, user algorithm is embedded in TMS320DM642 software system as task thread.
2.3 peripheral memory module
TMS320DM642 of this system will generate a large amount of data in the process of video image processing, and its internal RAM is only 256 KB at most, so it is necessary to expand large-capacity external memory to meet the needs of data processing. The system selects two pieces of SDRAM to store programs, data and cache digital video information, and one piece of flash memory to solidify programs and some user data that still need to be saved after power failure. SDRAM chip and flash chip are seamlessly connected through the EMIF port of TMS320DM642 [3]. The EMIF of TMS320DM642 has four independent addressable areas called chip enable space (ce0 ~ Ce3). When flash and FPGA are mapped to CE1, SDRAM occupies ce0, and a part of Ce3 is configured for synchronous operation of OSD function and other synchronous register operations in extended FPGA. The system combines to form a 64 bit long external memory port, divides the address space into four chip enabling areas, allows synchronous or asynchronous access of 8 bit, 16 bit, 32 bit and 64 bit to the address space, and uses chip enabling areas ce0, CE1 and Ce3. Ce0 is sent to the 64 bit SDRAM bus, CE1 is used by the 8-bit flash and FPGA functions, and Ce3 is set to the synchronization function.
2.3.1 SDRAM memory
The system uses mt48lc4m32b2 [4] to form SDRAM memory, with a size of 1m × 32 bit × 4 banks, 64 bit SDRAM bus is connected in ce0 space. The bus is controlled by external PLL driving equipment and operates under the optimal operation state of 133MHz. The refresh of SDRAM is automatically controlled by TMS320DM642. The interface diagram between EMIF and SDRAM of TMS320DM642 is shown in Figure 4.
2.3.2 flash memory
The system extends 4 m flash and maps to the low order of CE1 space. Flash register is 4 M × 8-bit am29lv033c. Flash register is mainly used to import, load and store FPGA configuration information. The CE1 space is configured to be 8 bits, and the flash register is also 8 bits. Since the available address space of CE1 is smaller than that of flash, three extension pages can be generated by FPGA. These extended linear addresses are defined through the flash basic register of FPGA, and the default value after reset is 000. The interface diagram of EMIF and flash of TMS320DM642 is shown in Figure 5.
2.4 OSD FPGA module
FPGA is responsible for completing the interface and control of all chips, including the interface between SAA7115 and I2C bus, reset control signal, EMIF interface and peripheral interface with TMS320DM642. Its architecture is shown in Figure 6. The chip model of OSD FPGA function module of the system is Xilinx xc2s300e-6pq208c [5], which is mainly used to complete the following work:
(1) Use TMS320DM642 external memory interface (EMIF) through registers;
(2) Use the EMIF interface of TMS320DM642 to control GPIO through the compileable register;
(3) Generating EMIF buffer control signals (DIR and OE);
(4) Provide continuous control interface for pll1708;
(5) Generate 3 pages of bit space for flash;
(6) Use the synchronization signal of SAA7115.
2.5 power supply and reset module
The system is powered by a single + 5V power supply, which is converted into + 1.4V and + 3.3V inside the board to power each device+ 3.3 V is the power supply of I / O port, decoder and other chips of TMS320DM642, + 1.4 V is the power supply of TMS320DM642 CPU core. The core voltage of TMS320DM642 is + 1.4 V and the peripheral I / O voltage is + 3.3 v. reducing the core voltage is mainly to reduce power consumption. The external interface pin adopts + 3.3 V voltage, which is convenient for direct interface with external devices. Since there are two different voltages, the coordination of power supply system should be considered. During power up, ensure that the CPU core power supply is powered up first, and power up at the same time as the peripheral I / O power supply at the latest. When turning off the power, turn off the I / O power first, and then turn off the kernel power. If the kernel is powered up later than I / O, internal bus contention will occur, resulting in unpredictable results. Therefore, the power chip tps54310 [6] is selected to obtain the above two voltages, and its power output effective pin PG and allowable voltage input pin en are used to ensure the power on and power off sequence of the core and I / O of TMS320DM642.
In order to prevent the system program from entering the dead cycle or abnormal due to voltage fluctuation, the system uses watchdog chip to control system reset. Here, TI's tps3823-33dbvt [7] watchdog chip is used. It is powered by + 3.3 V power supply and can monitor the power supply voltage. When the power supply voltage drops below 2.93 V, the reset signal is triggered to make the whole system enter the reset state until the power supply voltage is restored. The minimum length of the reset signal is 200 ms. At the same time, a watchdog timer is also included to monitor the jump edge trigger signal from the processor chip. If the trigger signal is not received within 1.6 s, it also makes the system enter the reset state for 200 ms, so that the system can be restarted after the system program enters the dead cycle. The connection diagram of TMS320DM642 power supply and reset circuit is shown in Figure 7.
3 anti interference Design
Since high frequency impulse noise is the most harmful to the system, the following measures can be taken to improve the anti-interference performance of the system:
(1) Optimize the design of PCB. In this system:
① Short and wide wires are used to suppress interference. The signal lines of clock leads and bus drivers often have large transient current, and their printed wires should be as short as possible. For discrete component circuits, the width of printed wire is about 1.5 mm to meet the requirements; For integrated circuits, the width of printed wires shall be selected between 0.5 mm and 1.0 mm;
② When transmitting multiple level signals, try to divide the level signals with similar front and back edges into a group for transmission; A large area of ground wire area is arranged on the back of the double-sided printed board, which can absorb and shield the high-frequency impulse noise generated by the components; Separate analog and digital power layers;
(2) Increase the anti-interference ability of the bus. The bus structure in the form of three state gate is adopted, and the pull-up resistance is connected to the bus to make the bus at a stable high level in an instant and avoid the suspension state of the bus.
Facing the real-time image acquisition and processing, this paper adopts the modular design idea and realizes the hardware circuit of the video image acquisition and processing system with TMS320DM642, SAA7115 and OSD FPGA. The system has the characteristics of simple circuit, compact structure, flexible adjustment, high reliability and strong real-time performance. Through verification, it meets the application requirements of the design, It can provide a reference for the further research and development of video image acquisition and processing in the future.
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