"As the Internet of things (IOT) gradually needs to perform more complex tasks, the storage requirements of IOT endpoints increase, especially those performing advanced edge computing. However, the upper limit of on-chip microcontroller flash memory is about 1 megabit (Mbit), and the memory demand of many high-end IOT endpoints is usually several times as much.
The traditional solution is to use external flash memory chip to expand the program memory of microcontroller, but when the memory requirement is up to 8 Mbit or more, it is often necessary to use off chip memory.
Therefore, in many cases, designers should simply ignore the on-chip flash memory and use a flash free microprocessor (i.e. no ROM microcontroller) combined with an external high-speed eight wire SPI in chip execution (XIP) flash chip, so as to significantly reduce the cost of the microcontroller and strengthen the scalability to improve the design guarantee. Due to the addition of high-speed eight wire memory interface, there is no need to worry about memory access time.
This paper introduces the ROM free microcontroller and external memory, and discusses how to make it a feasible choice in the Internet of things endpoint and embedded system that need large capacity program memory. In addition, this paper also NXP Semiconductors ROM free microcontroller and Adesto Technologies Taking the eight wire SPI XIP flash memory chip as an example, this paper introduces how to apply this concept.
Storage expansion of Internet of things edge endpoint
Most of the low-performance IOT endpoints use microcontrollers to manage the endpoints, and the firmware is stored in on-chip flash memory. Due to the addition of additional application code, wireless IP communication stack and enhanced security code, the firmware also needs to be expanded. Code expansion can be carried out in the development stage or in the field update.
Today, some IOT endpoints need to perform more computing functions. These IOT endpoints need to perform complex tasks such as sensor fusion algorithm, data interpolation, pattern or image recognition, and increasingly complex artificial intelligence (AI) computing, rather than just transmitting the original or partially processed sensor data to the central computer for processing through the network.
Therefore, the central computer only receives the local processing results of the IOT nodes, not all bytes of the original sensor data, so as to reduce the wireless network traffic. RF transmitter may be the most power consuming component in the endpoint of the Internet of things, so edge computing can often prolong the battery life of the battery powered endpoint.
In addition, systems that require on-site updates face other storage challenges. The memory requirements of conventional systems are at least twice the estimated program storage space to handle field updates. In this way, the existing program memory can be included and all wireless (OTA) updates can be processed. Some systems may need to estimate three times the program storage space and allocate the remaining memory to read-only factory firmware images. If a hacker attack or a specific type of system failure such as firmware image damage is detected, the system can load the factory firmware image to recover the system.
For some applications, memory expansion will soon exceed the embedded flash limit of 1 Mbit, so external memory must be expanded. In the past, the solution was to add external parallel flash memory chips. However, the disadvantage of this scheme is that it will occupy about 36 external pins of the microcontroller, otherwise these pins can be used for application I / O. In addition, it also wastes the space of printed circuit board and increases the possibility of electromagnetic interference (EMI) of circuit board.
SPI program memory extension
In addition to using the parallel bus, the serial peripheral interface (SPI) can also be used to expand the program memory. Traditional SPI only uses one data line for half duplex single bit transmission, but in recent years, the interface has been developed to support two and four data lines, which increases the data throughput accordingly, and finally makes it feasible to connect large-capacity external SPI flash memory chips.
For program memory applications, the traditional two-wire or four wire SPI uses shadow flash configuration to copy the external data flash memory to the embedded static random access memory (SRAM) and then map it to the program storage space. This can not only easily expand the program memory, but also run by high-speed SRAM to improve the execution speed. Although it has advantages, it also has disadvantages. Since the flash memory will be copied to the internal SRAM as needed, and the internal SRAM capacity is limited, the memory needs to be accessed in paging mode. Although adding on-chip SRAM can overcome this bottleneck, SRAM is one of the most expensive modules for any semiconductor, so the disadvantage of this move is that it will significantly increase the cost of microcontroller.
Recently, SPI has evolved into XIP. SPI XIP allows the microcontroller CPU to execute firmware code directly through external SPI flash memory. Adding cache in SPI XIP interface can greatly improve program execution speed.
Recently, the wide application of SPI XIP has led to the evolution of an interface supporting eight data lines. The throughput of this eight wire SPI XIP interface is significantly improved, and the running speed is much higher than that of on-chip flash memory, up to more than 100 Mbit / s.
SPI memory revolution
This has led to an unusual evolution back 30 years. Imagine a system with 1 Mbit on-chip flash memory and 32 Mbit external program flash memory that can be accessed by the eight wire SPI XIP interface. Such a small on-chip program memory raises the question: is it still a cost-effective system if the on-chip microcontroller flash memory is removed?
For a long time, it is generally believed that the medium performance system using flash microcontroller has higher cost performance than the non flash microcontroller with external flash chip. Only in recent years has this concept changed.
If the on-chip flash memory is removed, the cost of the microcontroller will naturally be reduced. The in-depth research and investigation show that if on-chip flash memory is no longer needed, the process and technical characteristics only used for flash memory can also be discarded, so as to reduce the manufacturing process cost and further reduce the cost of microcontroller. Therefore, the "ROM free" microcontroller introduced about 30 years ago reappeared. Nowadays, we call it flash free microcontroller.
(RE) introduction of flash free Microcontrollers
NXP semiconductors MIMXRT1052DVL6B ( Rt1052) is a high-performance flash free microcontroller that can make full use of flash speed. Rt1052 is NXP i.MX RT1050 One of the processor family products, based on 600 MHz arm ® Cortex ®- M7 with 32 KB instruction cache and 32 KB data cache. This microcontroller removes flash memory and adopts high-speed CMOS technology, which is not limited by internal flash memory, so as to achieve a clock speed of 600 MHz. Rt1052 has a large capacity SRAM of up to 512 KB, which can be partitioned as program or data memory.
The microcontroller has various high-end peripherals, including LCD interface, digital camera sensor interface (CSI) and pixel processing pipeline (PXP) supporting high-end cameras, SPDIF interface for digital audio, two USB OTG interfaces, two EMMC / SD flash card interfaces, two 20 channel analog-to-digital converters (ADCs) and an encryption module. The complete list of peripherals is shown in the block diagram (Figure 1).
Another option is NXP MIMXRT1051DVL6B ( RT1051)。 The function of this microcontroller is exactly the same as that of rt1052, but it does not have LCD interface, CSI and PXP.
The rt1052 has a flexspi interface and can execute code using a two-wire, four wire, or eight wire SPI XIP flash interface. In order to increase the security of the firmware, the microcontroller supports the connection of the encryption program memory through SPI XIP, which is provided by adesto technologies ATXP032-CCUE-T Is a typical example of encrypted memory.
New XIP flash operation
Adesto's atxp032-ccue-t is a 32 Mbit eight channel flash memory chip. Eight data lines support data transmission up to 266 MB / s in dual channel transmission rate (DTR) mode, which is much higher than that of on-chip microcontroller flash memory. The flash memory is powered by a 1.8 V single power supply, the typical eight wire mode standby current is 35 µ a, and the maximum SPI clock speed supported is 133 MHz.
During the effective reading of flash memory, the current consumption of atxp32 is 142 µ A / MHz, plus 1 mA current overhead (typical). In eight wire mode, the maximum SPI clock speed is 133 MHz and the current consumption is only 19.9 ma.
In addition, atxp032-ccue-t also supports standard SPI modes 0 and 3, as well as four wire SPI mode. The 256 byte security register contains 128 bytes of factory set unique identifier and 128 bytes of one-time programmable (OTP) memory, which can be used to store device information such as Ethernet media access control (MAC) address or security key.
The memory layout of atxp032-ccue-t is noteworthy. It is divided into four memory banks with a single capacity of 8 Mbit. The internal logic is pre configured so that the host microcontroller can execute code in one memory and program or erase in another. This operation is transparent to the host microcontroller and does not require special configuration settings.
In addition, atxp032-ccue-t also has three status and control registers, which can be used to configure device operating parameters such as low-power mode, enable or disable DTR mode, and set standard, four wire or eight wire SPI mode (standard SPI by default). By reading the status register, you can indicate the programming or erase operation status, the low power consumption status, and whether any memory is set as write protected.
Connect the flash free microcontroller with the external XIP
Connecting rt1052 with atxp032-ccue-t is quite simple (Figure 3). After power on, rt1052 starts to execute code in the 96 KB on-chip boot ROM. The boot ROM reads the status of 14 boot mode configuration pins, which can be used to select one of rt1052 multiple external memory interfaces to connect program memory. Optional interfaces include external EMMC card, micro SD card, conventional external parallel interface and SPI XIP (adesto's atxp032-ccue-t is used in this example).
The rt1052 boot option also includes downloading code from USB OTG or UART and executing by SRAM. In addition, during manufacturing, the boot mode option can also be set by fusing the internal fuse of rt1052 instead of using the boot mode configuration pin. As long as the boot ROM of rt1052 enables the eight wire SPI XIP interface for program memory execution, the program will be executed immediately. Next, the ARM kernel executes firmware from adesto atxp032-ccue-t in the same way as from an external parallel flash device or internal flash.
Since high-speed data transmission is involved, the eight channel serial flash memory should be placed on the printed circuit board as close as possible to the eight wire SPI XIP port of the microcontroller. In order to reduce interference, the length of printed wire shall not exceed 120 mm. The distance from the clock signal shall be at least three times the width of the printed line of the printed circuit board, and shall be far away from other signals to avoid interference. I / o [0:7] bidirectional data signal spacing shall be kept within 10mm to avoid offset.
summary
In view of the demand for edge computing, OTA update and related memory scalability, the memory demand of IOT endpoints increases. In some cases, designers may find it a good choice to use flash free Microcontrollers in these endpoint devices.
As mentioned above, the progress of flash free microcontroller, high-speed interface and eight wire SPI XIP flash chip provides developers with new options to build high-performance and cost-effective IOT endpoints or embedded systems, so as to replace the traditional flash based microcontroller method.
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