Video and multimedia systems are becoming more and more complex, so it is possible to obtain low-cost reliable IP checked for your system. In particular, video compression algorithms and standards have become extremely complex circuits, which takes a long time to design and often become a bottleneck of system testing and delivery. These MPEG-4 Simple PROFILE encoder / decoder cores may just meet the needs of your next multimedia system design.
application
MPEG-4 Part 2 is the latest standards in the following international video coding standards: H.261, MPEG-1, MPEG-2 and H.263. This standard was approved by ISO / IEC as "International Standard 14 496-2" (MPEG-4 Part 2). MPEG-4 Part 2 The video codec provides a superior foundation for a large number of multimedia applications. This standard provides a set of features and grades to meet a large number of different application requirements, such as frame size and using an error recovery tool. Examples of these applications include broadcast, video editing, telephone conference, security / monitoring, and consumer electronics applications.
The video coding algorithm used in the MPEG-4 Part 2 is developed from the previous coding standard. The frame data is divided into 16 × 16 macroblocks, each macroblock contains 6 8 × 8 blocks for formatting data in YCBCR 4: 2: 0. Motion can be used to estimate the prediction block from the previous frame by semi-pixel resolution. The discrete cosine shift (DCT) provides a residual processing function to create a more detailed view of the current frame. The simple compression standard provides a DCT coefficient of 12-bit resolution, and samples and reconstruct frame data for each sample 8 bits. MPEG-4 Emperor Efficiency is better than the previous generation of encoded efficiency used in MPEG-2 at a series of encoded bits.
Typical multimedia systems can use MPEG-4 in a larger system as a video compression component. An example of such a system is an end-to-end video conferencing system that can transmit compressed bitstreams between two or more participants. The names of these sources can change the system requirements, as the main speakers or attendees of the meeting may require higher resolution video and audio. This type of system can scale to video surveillance and security applications, and the display user can decide to use the inlay display to all video cameras, or to a camera view for detailed real-time analysis. These applications require streaming to perform at the receiver, and can process real-time viewing specifications.
The MPEG-4 decoder core can be built using a scalable multi-stream interface customizable for your application and system requirements, while the MPEG-4 encoder and decoder also support the maximum frame size specified by the user.
Architecture
Figures 1 and 2 show block diagrams of the MPEG-4 simple encoder and decoder core, respectively. These design uses hardware-based pipeline architectures, and a host interface is provided on the encoder to implement rate control of software control. With the included memory controller, the original capture sequence of the encoder and the reconstruction frame of the decoder are stored in the outer memory in which pixel data is accessed quickly and low. It also provides a simple FIFO interface for transmitting a compression bit stream, and the decoder can be built according to the user's specified number of bitstreams. It also includes a system interface to achieve maximum controlability and observability.
To create a scalable multi-stream design that meets different application requirements, the product package included with the core contains a large number of users to specify compile time parameters, allowing you to customize encoders and decoders. To create a resource efficient design, you can also set the width and height of the maximum support frame. Then the compiled design will contain enough memory and registers to support any frame size below or equal to these two parameters. Other parameters allow you to completely control the final design, and carefully build a system dedicated to your application.
Tables 1 and 2 list the FPGA resources for encoders and decoder cores based on different parameter settings for maximum support frame size and decoder input bitstream. All encoder design in Table 1 use 16 embedded XtremeDSP? Slice, and the decoder in Table 2 uses 32 embedded XtremeDSP slits. These design for Virtex? -4 components, these components contain a large amount of 18 kb selection SELECTRAM? Memory and embedded XtremeDSP slices. Other Compatible FPGA Series include Virtex-II, Virtex-II PRO, and Spartan? -3 device.
Note that the decoder design can automatically enter the number of fifo numbers and support multiplex / distributions according to the number of bit flow to be supported. The MPEG-4 encoder can achieve a throughput of about 48,000 macroblocks per second, providing a sufficient power that exceeds the simple grade 5 throughput specification. At the same time, the MPEG-4 decoder design can maintain throughput rate of about 168,000 macroblocks per second, providing two progressive SDTV (720 × 480, 60 fps) video streams or 14 CIF resolution video streams The sufficient throughput decoded. The decoder throughput is a grade 5 Simple encoder and a decoder core to be more than four times more.
in conclusion
MPEG-4 Simple encoders and decoder cores use unique, scalable, multi-streaming designs to meet your specific system requirements. A large number of different applications can utilize these cores in multimedia systems, including video conferencing, security and monitoring, and any exciting new consumer applications you want to display to the world.
These video designs use high throughput, pipeline architecture, and sufficient custom-made parameters to create efficient design dedicated to your application. Read more
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