1 Introduction
As the high-speed development of digital signal processing, the processing of analog signal has been replaced by digitization. However, the resolution of digital system is increasing, and as the core one A / D converter of analog-to-digital conversion system, its precision and sampling rate have also increased. However, the accuracy and sampling rate are a pair of contradictions, which is difficult to meet the requirements simultaneously, so become a bottleneck that restricts the development of A / D sampling system. The presenter of the time cross-sampling program has broken through the limitations of a single A / D converter performance, and multiple high-speed A / D conversion calendar alternate sampling is an effective way to improve system sampling rates. In a plurality of parallel A / D converter sampling systems, signal reconstruction is quite strict in sampling clock precision, and the simulation method of the conventional crystal oscillator plus displacement circuit and the filter circuit cannot meet this requirement. This paper proposes that the clock distributor AD9516 provides a sampling clock to the four time cross A / D converter.
2 Introduction to devices and their configuration
2.1 AD9516 Introduction
The AD9516 is a clock dispenser that is integrated with a low phase noise clock and a low jitter 14 channel clock allocation function. It integrates 1 integer N divided frequency synthesizer, 2 reference inputs, 1 pressure control oscillator (VCO), adjustable delay lines, and 14 clock drivers, including LVPECL, LVDS, and CMOS output. In addition, the in-chip-integrated VCO improves system reliability. The 14 output channels can be 6 (3 pairs) clocks, respectively, 1.6 GHz LVECL output and 4-way (2 pair) clock up to 800 MHz LVDS output, LVDS clock outputs two channels of up to 200 MHz CMOS Output.
2.2 Pin Description and Peripheral Circuit Configuration
Ren_sel: Reference selection. The AD9516 has two reference clock inputs with REFL and REF2, which is used to define a system using REFL input (pulverity) or Ref2 (high) reference signal.
SCLK, CS, SDI0, SD0: serial port synchronization I / 0, compatible with the SPI protocol, implements communication with the AD9516 internal register. SCLK is the clock input; CS is a chip select signal; SDIO is the host output / AD9516 input (rising edge of SCLK), or host input / AD9516 output (SCLK falling edge); SDO is the host input / AD9516 output.
REFMON, LD, STATUS: Status output for testing the internal signal of the AD9516. Three registers are changed by changing 0x17, 0x1a, 0xLb (address of the internal register). Test the output clock of the VC0 and the divider to obtain the current AD9516 operating state.
LF, CP: External ring filtering, can provide feedback voltages to the internal VCO.
OUT6, OUT6, 0UT7, OUT7, 0UT8, OUT8, OUT9, OUT9: Output 4 LVDS clock, can provide a sampling clock to the A / D converter.
The above-mentioned function description of the main pins of the AD9516, and some feature descriptions including input voltages, reset and other pins can be seen. According to the above main pin description, the external circuit configuration diagram of the AD9516 is given, as shown in FIG.
2.3 Internal Register Configuration
The AD9516 can set three working modes, including external VC0, external CLK, and internal VC0. This system is designed with internal VCO and reference input frequency mode of operation.
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2.3.1 Working principle of PLL
Reference input (REFL input) First via the R divide module (14-bit register), then enter one end of the PFD (phase / frequency monitor) module by R delay module (delay adjustable), and the signal generated by the VCO passes N points Frequency module (Pred-frequency module P.P + 1 and A / B counting module) and N delay module (delay adjustable) enter the other end of the PFD; PFD is used to compare the frequency and phase difference between the two signals. Generating a signal transmitted to a ratio to the CP (charge pump), the charge pump is connected to the control terminal of the VC0 through an external annular filter. The charge pump charges (placed) the connection node of the ring filter to the ring filter of the PFD to reach the VCO voltage modulation program, so that the frequency and phase of the PFD are fully matched, and the phase is latched, and the output synchronization is latched.
2.3.2 Configuration of Division Register
In addition to the registers R, A and B, which are used to generate a stable VCO, and the frequency division register further includes a clock output division register, a divided register of each pair output channel. The clock output frequency divider can be set to any integer in 2 to 6, and each of the output channels can be used as a divided parameter using any integer in 1 to 32. It should be noted that the configuration of the three registers of PLLs, the configuration of these registers, must be reasonable to configure the VCO to operate within the frequency range provided by the reference input, otherwise it will not be latched. Module module. These constraints include: PFD (phase / frequency monitoring) input frequency range, A and B counters input maximum frequency, A and B values. In design, considering these constraints and designs need to be configured correctly.
2.3.3 Output Phase Register Configuration
Adjust the output phase: including the phase delay coarse tuning and phase delay.
(1) Phase delay is coarse
Since the system requires a four-way 110 MHz sampling clock having a difference of 90 °. The OUT6 is a phase reference signal, then OUT7 is relatively delayed 90 °, OUT8 is relatively delayed 180 °, OUT9 is relatively delayed 270 °. Since the four LVDS output is 2 pairs, each pair of shared two divider. OUT6 is shared with OUT7, OUT8 is shared with OUT9. The divider of the AD9516 can be used in phase delay. Therefore, the divider shared by OUT8 and OUT9 can be set to 180 °, and when the phase is detailed, only the 0UT7 delay is 90 °, OUT9 delay 90 °.
(2) Phase delay is fine
For OUT7 and OUT9 relative to OUT6 and OUT 8 delayed 90 °, by adjusting the AT micro delay module of each output channel, the phase delay is detained by the capacitance charge and discharge of the ΔT module, delayed The time can be calculated by capacitance and current value.
3 Software Programming
According to the working principle of the AD9516, all registers are properly configured, and the data needs to be loaded into the AD9516 internal register. The load mode of the AD9516 is a serial port synchronous load, compatible with the SPI standard protocol and SSR protocol, and serial controlle allows the configuration of all registers of the AD9516 to read / write, support single-byte and multi-byte and high / low priority sequence mode, The AD9516 serial control can be configured as a single dual I / O pin (SDIO) or two one-way pins (SDIO / SDO) mode. In the default mode, the AD9516 is loaded for dual-end mode, and the load clock is SCLK.
In order to facilitate debugging, the DSP is the core of the entire read and write operation, whether it is reading data or written data is completed by DSP. The software process of writing the AD9516 is to store the value of the write register in the ROM of the FPGA, and the DSP reads data from the FPGA via the slow protocol. Then written to the write module of the FPGA via the DSP, and finally written to the AD9516. The software flow of the AD9516 is based on the read sequence of the AD9516, and is written to the read command, and finally the AD9516 register value is read by the read module. The specific FPGA design is shown in Figure 2.
After completing the FPGA design, since the entire system control is completed by the DSP, the DSP is required to program. The program code for writing the AD9516 of the partial DSP (TS 1 201) is given below, where the system register is configured to 0x189067: 64-bit bus, slow protocol.
Finally, according to the FPGA design, the software simulation of writing the AD9516 module is shown in Figure 3 using the Quartus II simulation. FPGA uses an EP2S60F672 device for Ahera's StratixTM II series. Its simulation results are completely consistent with the writing timing of the AD9516.
4 conclusion
Cross Sampling System Clock Source Performance is the key to determining the entire sampling system indicator. Based on this, this paper proposes a design plan for providing sampling clocks to high speed A / D conversion using AD9516. Practice has proved that the clock generated by this method can meet the four-channel A / D conversion to achieve 440 MHz cross-sampling clock requirements for other high-speed A / D conversion designers.
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