Digital 100 Billing Decrease Counting Circuit, DIGITAl Counter
Keywords: digital counter circuit diagram
Author: Zege Zeng Dezhi
The circuit structure is shown in a picture, mainly consisting of a crystal oscillation circuit, a frequency division circuit, a control circuit, a counting circuit, a decoding circuit, and a digital tube display, etc. Working principle 1 The signal is divided by the IC2 (integrated trigger 74LS73), and the square wave signal of 1 Hz is output as the count pulse of the counter, and the counting of the counting counter IC4 is sent. R1 in the oscillating circuit is a feedback resistance; its value is large (10mΩ) facilitates improving the stability of the oscillation frequency. Capacitors C1, C2 and crystals constitute a resonant network to achieve control of oscillation frequencies, and provide 180 degree phase shift, thereby constituting a positive feedback network to satisfy the oscillation condition and operates normal. 2, count: Count circuit consists of two 74LS190 (IC4, IC5) to count the counts and ten digits. The 13-pin of the IC4 carries the carry-on / borrowing output) and the 14 pin (count pulse input) of the IC5, complete the function of the bit to ten bits or borrowing. 3, decoding and display: This part of the circuit consists of two 74LS48 (IC6, IC7) and two digital tubes, IC6 performs an 8421BCD code outputted by the bit count circuit, the digital tube display, IC7 pair ten digits Circuit output 8421BCD code for decoding drive, digital tube display. 4. Control circuit: It is mainly composed of three buttons SB1, SB2, SB3, and a double JK flip-flop 74LS73. 1 addition count control: Turn on the power supply, since the voltage at both ends of the capacitor cannot be mutated, the IC3A, IC3B CLR = O, so the two triggers are cleared, ie 1Q = 2Q = O, 1Q = 2Q = 1, 2Q = 0 is sent to the CLR end of IC2, which makes it clear. At this time, the IC2 is not counting the pulse to output to the counter 74LS190, and the signal is sent to the 74LS190 enable control terminal due to the q (reverse) = 1 of IC3B. (CTEN), the counter is operated in the hold state, so the digital display is unchanged after powering. The LOAD of the SB2, IC4, IC5 changes again, so that IC4, IC5 is in parallel input state, and because of A = D = u / d = 0, b = c = 0, IC4, IC5 QA = QB = QC = qd = 0, then it is displayed as 00 (set up), then press SB3 (start) to enable the IC3B to obtain a falling pulse, then the IC3B output is flipped from O to 1, so that the IC2 output counts the pulse, sent to IC4, Because of the q (inversion) of IC3B, the CTEN = 0 of IC4, IC5, at this time, although C4 becomes high, the IC3A has no fall pulse, and the Q remains 0, then U / D = 0, so IC4, IC5 starts to make an additional count. It can be seen from the cascade relationship of IC4 and IC5, and the inlet output signal of IC4 is a count pulse of IC5, and when a bit count to 9, the tenth CP pulse rises to time. RCO / BO has inlet pulse output to ten, ten bits start counting. When counting to 99, the 100th pulse arrives, the digital display is 00, completes a 100-en-additive count function.
During the counting process, if you stop counting, press SB3 to obtain a falling pulse, and the output terminal Q is flipped to 0, Q (inverse) = 1, the IC4, IC5 CTEN = 1, the counter stop counting Intentional, then SB3- times, then count, to achieve pause / start function. 2 subtraction counting control: After the power is turned on, the IC3A, IC3b, IC2 are cleared, then press SB1, D1 to turn on, because C3 is small, discharge is very fast, so IC4, IC5 LOAD terminal becomes low Then they are in the parallel input state, and the IC3A is triggered. Q is changed from 0, then A = D = U / D = 1, B = C = 0 (ground), the QAQBQCQD = 1001, the number is drifted , Display 99 (set 9), then press the SB3 (start subtraction count) IC3B is triggered, q is changed from 0 to 1, IC2, output counting pulse, q is changed 0, so IC4, IC5 CTEN = 0, Then the count starts to subtract down, if you need to pause, press SB3. It can be seen from the cascading relationship, and the thirteen feet of the IC4 outputs the borrow pulse signal. 3 The mutual conversion control of the addition and subtraction is calculated to be a subtraction count, then it is turned to subtraction count, then the IC3A's Q terminal is flipped, from 0 to 1, then A = D = u / d = 1, and LOAD = 0, then the digital tube is reset 99, then press SB3, start subtraction count, and then it is. 4 Protection circuit: The access capacitor C3 is to avoid the trigger IC3A trigger, due to delay flipping, and the low level of the IC4, IC5 is quickly disappeared as the button is reset, resulting in no 00 or no 99, access After C3, after the SB1 and SB2 reset, it is necessary for a period of time due to C3 charging, so that the LOAD maintains a low level, waiting for the delay of the IC3A to prevent competitive adventure. Diodes D1, D2 are isolated, so as not to interfere with each other between SB1 or SB2, interference between interference or integrated circuits. 5, indicating the circuit: The LED is the addition and subtraction count indicator. When it is calculated as an additional count, the LED illuminates, the LED does not illuminate. The main component IC1 is a 4060 gravity divider, IC2, IC3 is two 74LS73, IC4, IC5 is two 74LS190 beaters, IC6, IC7 is two 74LS48 decoders, which are shown as two copies of cathode digital tube. It is known from the above analysis to do additional counts or subtraction counts, which can be used for digital display circuits or countdown. By making the circuit, the design and production of love digital display circuits is improved.
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