Digital signal, power supply, and ground circuit design based on RF matching network based on CMT2300A

The "CMT2300A-based RF Match Network Circuit Design" and "CMT2300A-based switching RF matching network circuit design" we talked about several aspects when designing RF matching network: port impedance matching must Consistency, insertion loss is small as possible, with external decline is as large as possible, PA power and efficiency are as high as possible, and the number of components is as small as possible. Designed for CMT2300A RF matches, there are two matching methods of Direct Tie and Switch Type. Today, we will not pay attention to the circuit design of direct and switching radio matching networks, and should also pay attention to digital signals, power supplies and ground circuit design. The traverspread of digital signals (including serial ports and GPIO ports) are as follows: 1. Digital signals should be as far as possible away from crystals and RF traces. 2. The digital signal should be surrounded by the ground as much as possible to reduce mutual crosstalk. 3. The serial CSB, FCSB, SDIO, SCLK pin are easily interfered with the unreasonable line of wiring, and the larger the power output (20dBm), the lower the operating frequency, the greater the probability of interference. Power filter circuit design In order to reduce the impact on the noise pattern on the power supply, the user should design filter capacitance in the following effects of the PA output on the power supply. 1. C10 is close to the AVDD pin of the chip. 2. C11 is close to the DVDD pin of the chip. 3. C12, C13 is close to the choke inductance, suggesting that C13 is reserved to deal with high harmonics. 4. C14 Recommended value 4.7 - 10uf based on the performance of PA output power and power supply circuit. Laying design described as follows: 1. Reference stratum: RF trace needs to be continuously performing reference planes in adjacent layers to achieve efficient power output and optimal reception sensitivity. 2. Both the radiofrequency traces are packed and tied to the reference ground plane to reduce stray radiation. 3. The networks in each layer have hit the holes to the reference formation, reduce the loop path, thereby reducing the radiation of the circuit. 4. The edges of the circuit board are as close as possible, and the via pitch does not exceed λ / 10, thereby reducing radiation and enhancing anti-ESD capabilities. 5. The IC substrate must have several via to the formation, which is conducive to the improvement of the radio frequency performance indicator of the chip. 6. The crystal circuit is sensitive to interference and is isolated by a package.

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