To put it, the ESP32 is not strange for the current engineers, but the two are still unexpected, but think about it. How to say, ESP32 can be said to be one of the most popular wireless communication modules that are currently doing DIY enthusiasts, and because of the WiFi / BT function, followed by the price; and RISC-V is also In the past two years, one of the most popular microcontroller architectures in the past two years, and the combination of the two is also a water to the stream to the streamlined command set.
Does anyone remember the HiFive1 development board launched in 2017? It is the development board (evaluation) of the world's first commercial SOC FREEDOM E310-G000 (referred to as FE310) based on the world's first commercial SOC FREEDOM E310-G000 (Evaluation) (Evaluation) (this company is also RISC) The -v architectural instruction set founded), the company's HiFive1 upgrade version of this company is about to introduce, Hifive1 Rev B, combined with an ESP32 and RISC-V a development board.
The difference between HiFive1 Rev B and HiFive1
At first glance, it will find that HiFive1 Rev B and HiFive1 is the biggest difference in adding an ESP32 module, just this? of course not.
The following figure is HiFive1, or it can be called 1 generation.
The picture below is an upgraded version of Hifive1 Rev B.
The changes on the development board are mainly shown in the table below:
Core SOC upgrade
The SOC mounted by the developer is upgraded from the 1st generation of Fe310-G000 to Fe310-G002 on the HiFive1 Rev B version.
The improvement of this upgrade is still obvious, and the Fe310-G002 adds support for the latest RISC-V debug specification 0.13, hardware I2C, two UART, and power destination for the core rail in low-power sleep mode. Like the original Fe310, Fe310-G002 uses Sifive's E31 Coreplex processor, high performance, 32-bit RV32IMAC kernel, 16KB L1 instruction cache, 1 KB data SRAM register, and hardware multiplication / division.
The Fe310 runs from 320 + MHz, which is one of the fastest microcontrollers in the market.
More peripheral devices
With the second generation version, the Fe310 chip now has built-in hardware I2C peripherals and additional UART (two), which opens the door to other devices such as various third-party sensors, peripheral modules. In addition, the USB debug interface has also been upgraded to Segger J-Link, supporting drag and drop code download.
Low power sleep mode
Fe310-G002 has a normally open (AON) power domain from 3.3V. By AON control, the CPU kernel power rail (1.8V) can be turned off in sleep mode and open when it detects awake events.
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Wireless connection
The HiFive1 Rev B board has Wi-Fi and Bluetooth features, which is attributed to a single core ESP32 coprocessor, which is a wireless modem for the FE310-G002 processor.
On-board storage
It is worth discussing that the original 16MB QSPI NOR FLASH has become 4m. Although the 16MB space of the initial generation is too large, even if it is replaced with 4MB, the storage space of the code is still more than, but it is always made of people, this is not a product, this is the development platform, which means there are many unlimited possibilities. Toss, always have redundant performance or function to the user, so that it is tossing enough to taste enough.
One More Thing: Open Source RTL
As the first open source commercial RISC-V SOC, SIFIVE has contributed the Fe310 RTL code to the open source community. Now, we can completely see the structure inside the chip, understand the hardware work, RTL code let the business or engineers customize their own SOC on the basis of Fe310, this measures are undoubtedly SiFive wants to encourage global companies or engineers in RISC-V Software running your own or open source development based on new hardware based on RISC-V.
summary
Open source is king!
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