Due to the large amount of data acquired by the image acquisition system, the bandwidth requirement is high, and the previous image acquisition system is usually implemented using the PCI bus. However, the number of PCI interfaces configured in the computer itself is very limited, and the disassembly of the PCI interface device needs to open the chassis, and the general operator does not have such an capability, resulting in system applications. USB (Universal Serial Bus) Interface Column can completely solve the above problems. First, the speed of the USB2.0 interface has reached 480Mbps, which can fully meet the speed of the image acquisition system. In addition, the USB interface is really supporting plug and play, and allows thermal plug-in interfaces, so currently a large amount of data acquisition system has chosen to use USB2.0 interface implementation.
This paper utilizes SAA7113H to implement analog video signal decoding, and transmit digital image data directly to the computer by using the EZ-USB FX2 microcontroller CY7C68013, through the USB 2.0 interface, through the PC program to achieve image loss, greatly simplify the hardware design of the capture card, Reduced the hardware requirements of the acquisition card, effectively reduce the cost of the image capture card.
1 system hardware design
The system hardware structure is shown in Figure 1. The system is mainly composed of video decoding chip SAA7113H, USB control chip Cy7C68013 and a capacity of 1 kB 24c01eep chip.
Be
Be
Figure 1 System hardware structure
1.1 Video Decoding Chip - SAA7113H
SAA7113H is a video decoding chip from Philips, which is to decode the input analog video signal as a standard 8-bit VPO digital signal. It can enter 4-way analog video signals, which can be converted to 4 composite video inputs to different configurations of the I2C bus to change brightness, contrast and other parameters. SAA7113H compatible with PAL, NTSC and other formulations, automatic detection field frequency, can automatically switch control between PAL, NTSC. The SAA7113H decoded is output to the standard YUV 4: 2: 2 format digital signal.
1.2 USB control chip - CY7C68013A
CYTC68013A (EZ-USB FX2) is a USB2.0 chip introduced by Cypress Semiconductor. It integrates an enhanced 8051 kernel, supports a maximum 48MHz clock frequency. At the same clock frequency, the average command of FX2 can be achieved. 2.5 times the standard 8051. The CY7C68013 chip is integrated with an independent SIE (serial interface engine) with the 8051 kernel, and implements the external data and the USB port data exchange with the USB port and the external logic to share FIFO without the need for 8051 kernel participation. The speed of data transmission is greatly accelerated, and the maximum speed can be achieved is 480 Mbps.
1.3 System hardware implementation
In terms of hardware connection, 24c01 is connected to the I2C port of CY7C68013 to extract information in 24C01 after power-on, and realize the device enumeration, download the corresponding firmware. With the CY7C68013 analog I2C port connection SAA7113H, the internal register is configured to implement the decoding chip initialization operation. The CY7C68013 operates in the SLAVE FIFO mode, connects the VPO data bus of the SAA7113H directly to the FD bus of the CY7C68013, and detects the field flag signal of the digital video using the IOAO port of CY7C68013, which is used to implement frame synchronization. The amount of SLWR * (dependent write) and SLOE (output valid) of the CY7C68013 are set to be invalid, and the digital video signal is directly written to the CY7C68013 by the SAA7113H 27MHz synchronous clock. FIFO, then use SIE to transfer data in the FIFO to the PC in a high speed, to achieve the acquisition of video data.
2 system software design
System software design mainly includes firmware programming, driver design, and most of the PC acquisition procedures.
2.1 firmware programming
The firmware program flow chart is shown in Figure 2. The firmware initializes Cy7C68013 after the capture card is powered on, so that it operates in the SLAVE FIFO mode, and the number of bus bits is 8 bits to receive the 8-bit digital video signal of SM7113H. Set the EP2 endpoint to a batch auto IN transmission method, 512 bytes 4x FIFO buffer. One maximum transmission packet size is 512 bytes. Synchronous slave write data is implemented using SAA7113H clock signals.
Be
Be
Figure 2 Firmware Flow Diagram
The SAA7113H is initialized by the simulated I2C port, allowing it to receive an analog video signal of the CCD camera, output in a standard ITU 656 format, and set the RSTO output parity field, and then wait for the start to collect commands of the host computer.
After receiving the PC start image acquisition command, the firmware program first checks the parity field signal of SAA7113H through the IOAO port. If the external analog video signal is not connected, the signal will continue to maintain a high level. The firmware waits and confirms that the external video signal is not connected, otherwise it has been emptied to clear the FIFO, which will be cleared in the FIFO, until the yard signal arrival, firmware return equipment Prepare information to PC to achieve video image frame synchronous acquisition. The image data transfer process will be fully controlled by SIE, and the firmware does not participate in the transmission operation.
2.2 Driver Design
A universal driver is provided in the CYPRESS development package, which is cyusb.sys, which is in line with the Windows hardware quality laboratory WHQL standard, and the system uses the driver to implement image data acquisition. Since the CY7C68013 is a soft configuration, there is no memory for permanently storeing the firmware program, and the firmware program needs to load or load it from the PC after each power-on or downloaded from the PC to the internal RAM. The driver mainly implements the loading function of the firmware program so that the system can automatically load the firmware to CY7C68013 from the PC machine, and then use the universal driver to complete the device of the capture card.
A firmware download drive template provided in the development package provided in Cypress, that is, EZ-Loader Driver. System Firmware Download driver mainly rely on it. The specific steps are:
1) Use HEX2C.exe to convert the Intel HEX format file to the C code array.
2) Copy all EZ-Loader Driver files together with subfiles into a new directory. And use the first step C code array to replace the arrays in Firmwa Re.c in EZ-Loader Driver.
3) Creating a firmware download driver in a new directory in a WindowsXP DDK.
4) Rewrived the driver installation information file. Technology area
Tektron supports Amazon (AWS) media service, providing quality assurance for end-to-end video
IMEC is about to shock the first short-wave infrared (SWIR) band hyperspectral imaging camera
4K super high-definition home theater projector brings HD experience, full of fun
Video display system design based on unified calculation architecture technology
Apple TV 4K dismantling report: familiar modular components
Our other product:
