Keywords: frequency meter circuit diagram
Author: Wu Huan
First, design ideas
The frequency measurement range 0Hz ~ 999Hz, the measured voltage range is 0 ~ 7mV, the circuit structure is simple, the cost is low, and it has great help to improve the ability to enhance the theoretical knowledge. This circuit can be roughly divided into two parts: analog and numbers:
The analog portion includes a signal amplifying circuit, a signal shaping circuit; a digital portion includes a counting circuit, a display circuit, a time base signal generating circuit and a counter and a latch control circuit, and the basic frame as shown below. The overall idea of this circuit is to convert an alternating analog signal into a digital signal, and then implement the frequency calculation. When the input of the circuit is input to the input of the simulation signal. After the amplification circuit of the first part is enlarged. Then, shaped by a plastic circuit consisting of a comparator. At this point, the signal outputs the signal becomes a rule-to-rank, and finally the count function is implemented by a digital circuit. The digital signal can be processed by a digital circuit such as a counter. The counter is connected to the display circuit. The measured frequency can be displayed. The function of the time base signal generating circuit is a time base signal for a second pulse width to control the counter to implement a second count, and the time base signal also controls the latch circuit, and latches data in time after the count ends. Stable display.
Second, the principle of circuit
The system circuit is shown below.
(1) Amplification circuit: The amplifier circuit is mainly composed of an LM324 integrated op amp and peripheral components. The amplification circuit uses two-stage amplification. The gain of the first stage signal is 20 dB. The second stage signal gain is 40 dB, and the magnification of the two level is 1000 times, and the bandwidth of its frequency is from 0 to 5 kHz. The communication band of the amplified circuit can be improved by multi-stage magnification, and if the measured signal frequency is high. Multi-stage enlargement can be used to increase the passband, depending on the actual situation, due to the low frequency range of the circuit, there is no much requirement to pass the frequency band. In Fig. 2, the A terminal is an input of the measured signal. The B end is the output of the amplified circuit, and the input of the control circuit is connected. (2) Plastic circuit: The main function of the plastic circuit is to shape the altered signal of the first part into a digital signal (ie, a square wave signal of the amplitude 5V), and the circuit is mainly composed of the comparator. In this circuit, we choose LM393 comparison The B-terminal is the integrated circuit input, and C is the output terminal of the plastic circuit. (3) Counting circuit: Counting circuit part We use the cascade of 3 pieces of decimal additive counter 74LS160 to realize the frequency display of 0-999 Hz, 74LS160 is a preset decimal synchronous counter, using its cascading, can constitute an arbitrary counter. 74LS160 (a) 2 pin is the input of the pulse signal, 1 foot-to-end. 74LS160 (a) of CO carrying 74LSL60 (b) of CLK pulse; in the input, 74LS160 (B) carrying 74LS160 (c) CLK pulse input, three counters PE, TE and LD termination power supply. The counter is made to the count, the CLR terminal is connected, and the count is controlled by the time base circuit. (4) Display circuit: The display circuit portion is mainly composed of two 74LS273 latches and 12 red light-emitting diodes, and 74LS273 is an 8-bit data / address latch. He is a 8D trigger with a clear function, mainly to lock the output signal of the count circuit, because the frequency of the counter is faster. Using dynamic display, we are easy to observe for the stability of display, so latched in the output of the counter. The latch signal of the latch is provided by the time base circuit, and when 1 pin is high, the 11 (CLK) pin is a latched control terminal, and is a rising edge trigger lock, when 11 feet have a rising edge Immediately lock the data of the input feet 3, 4, 7, 8, 13, 14, 17, 18, and immediately present the output foot 2 (Q0), 5 (Q1), 6 (Q2), 9 (Q3), 12 (Q4), 15 (Q5), 16 (Q6), 19 (Q7). The CLR end of 74LS273 is connected to the high level, so it works in unclear. (5) Time-based signal generation circuit: The main function of the circuit is to generate O. The 5Hz time base signal (ie 16 seconds, a pulse width of 1 second) provides a latch signal for the latch and provides a counting gate signal for the counting circuit, and implements the frequency count and display. The time base signal generating circuit is composed of a frequency of 3.2768 MHz and a piece of CD4060 divider and a peripheral component. CD4060 (IC) is a 14-level divider circuit with an oscillator. External R, C components or quartz crystals and capacitors are used as the oscillator. The internal contains two non-door and 14-level 2 divided circuits, which produces a signal frequency of 32768 Hz, and after the 14-stage two-point frequency, a 2 Hz pulse signal is obtained. The following image is the output of 2 Hz signal.
(6) Counters and latch control circuits This partial circuit is mainly to control the clearance of the counting circuit, the count and the latch display of the latch circuit. The core device of the circuit is a D-flip-flop 74L. S74 is composed of a piece of non-door 74LS00. H is a 2Hz square wave signal (ie, the input terminal I, J of the cycle is 0.5s, time base circuit), the output of the control signal, the CLK clock end of the clearance of the counter, the latching circuit, H, I The signal timing of the J side is shown below.
After the reference signal is divided by the D trigger, the square wave signal of 1q and 2Q is obtained, and the square wave signal of the L-terminal and the J end can be obtained via two and non-ends. When the signal of the L-terminal is operated in the count state at the high electrometer, the counter is cleared to the counter. When the signal of the L-terminal is in the falling edge, the signal of the J end is in the rising edge. The rising edge signal starts the latch until the next rising edge arrival. This makes the count and latch of the input signal. (7) Power circuit: The overall power supply of the circuit requires dual 5V, so we can design a simple dual power supply circuit. The schematic diagram of the circuit is shown below.
Third, experience experience
The circuit is easy to understand, and the components are easy to choose. The circuit mainly involves many professional knowledge such as digital electronic technology and analog electronic technology, and counter, through the design and construction of this circuit, it can realize the knowledge learned by the book while improving the hands-on ability. During application to practice, the effect of combining theory and practice is achieved. Interested readers do not prevent personal practice.
Our other product:
