This paper is an industrial fieldbus and Ethernet interconnection method, which introduces the design and implementation of the protocol conversion gateway between the Ethernet and the CAN fieldbus. The AT89C55 is used as the main processor, and the CAN bus and Ethernet are implemented through two interface chips. Even, give their hardware structure and software design ideas. Provide a feasible method for enterprise information networks and control network integration.
1 hardware structure
At present, there are two main methods for embedded gateway design for CAN and Ethernet: one is the design method of low-end MCU plus interface chips, the other is a high-end MCU plus EOS (real-time multi-task operating system) plus interface chip Design method. Because CAN only uses the ISO / OSI reference model, the second floor, the agreement is relatively simple, and is suitable for discrete control systems with low cost and low rate requirements. From a reasonable cost and effective utilization processing capability, the design uses a method of low-port MCU plus interface chip, and its hardware block diagram is shown in Figure 1.
Figure 1 Hardware schematic
1.1 Main Control Chip and Ethernet Interface Module
According to the requirements, the system selects AT89C55 microcontrollers produced by ATMEL companies with high performance prices. It is a measuring object and embedded application, so its architecture and CPU, instruction system, peripheral unit circuits are specifically designed according to this requirement. It has a Flash program memory of up to 20 kB, and the AT89C55 is fully compatible with 8051 instruction set. On-chip Flash is convenient for online programming, the operating rate is up to 33 MHz, 256 B, 32 programmable I / O Port, 3 16-bit timing / counter, 8 interrupt sources, support low-power idle mode of operation. The Ethernet interface is the RTL8019AS chip, which is a highly integrated Ethernet controller produced by Realtek, which enables all the features of the Ethernet Media Access Layer (MAC) and Physical Layer (PHY). There are two RAM regions inside the RTL8019AS: one is 16 KB, the address is 0x4000 ~ 0x7FFF, you must receive and send the packet to read the 16 kb RAM of the RTL8019AS through the DMA, which is actually a double port RAM, that is, there are two The bus is connected to its connection, a bus is used for RTL8019AS read / write or write / read the RAM, namely local DMA; another bus is used for single-chip, the remote DMA; the second is 32 bytes, the address is 0x0000 ~ 0x001F for storing the Ethernet physical address. The principle of the hardware interface chip of the main control chip and the Ethernet interface chip is shown in Figure 2. It is worth noting that because the Ethernet package can be more than 1,500 bytes, only 256 bytes of the AT89C55, so that such a large package cannot be stored, so it has expanded a 32 kB of external RAM, so at the same time It is also possible to improve the data transfer speed of the microcontroller.
Figure 2 Ethernet interface circuit schematic
1.2 CAN interface module
The main device that makes up the CAN system is a CAN controller and transceiver. In this design, the CAN interface module uses SJA1000 chip and PCA82C250 chip. The SJA1000 is a separate CAN controller that is an alternative product of another CAN controller PCA82C200, which is Philips, which has added a new working mode (PELI CAN), which supports the CAN 2.0B protocol. The SJA1000 mainly completes the communication protocol of the CAN to implement the assembly and splitting of the packets, and receive filtering and verification of information.
The PCA82C250 is an interface between the CAN controller and the physical bus, mainly used to enhance the driving capacity of the system. In a transceiver system, the number of nodes can at least 110, and also reducing radio frequency interference (RFI) and strong anti-electromagnetic interference (EMI) capabilities. When processing this part of the circuit, there are several places to pay special attention:
(1) Question of the crystal circuit. 89C55 and SJA1000 should have their respective independent crystal circuits that cannot be driven with the SJA1000 clock output signal CLKOM.
(2) The problem of reset pin. Although the reset of SJA1000 is low, it cannot pass a non-door to directly connect the backup pin. There are two ways to solve the reset pin problem: the first is the use of the I / O pin using the microcontroller's I / O pin, which is the advantage that the single-chip can fully control the reset process of SJA; the second is suitable Reset chip, in order to reduce cost, the design takes the first method.
(3) The potential of the RX1 pin must be maintained on approximately 0.5 VCC, otherwise the logic level required by the CAN protocol will not be formed.
(4) Be sure to pay attention to the terminal impedance matching of the cable, which directly affects whether the CAN bus can work and network performance. The hardware circuit diagram of the CAN interface module is shown in Figure 3, and there is a slope resistor R on the RS feet of the PCA82C250, and the size of the resistance can be appropriately adjusted according to the bus communication speed.
Figure 3 Hardware circuit diagram of the CAN interface module
2 communication module software design
2.1 implementation of the SJA1000 driver
The SJA1000 driver is made of an initialization function of SJA, a transmit function, and a reception function, and FIG. 4 is a flowchart.
Figure 4 SJA1000 driver flow
(1) Initialization of SJA1000. The SJA1000 needs to be initialized after the system is powered, the hardware reset, or the main controller issues the reset command to set important parameters such as working mode, communication rate, output control method, and identifier masking format. The initialization of the CAN controller SJA1000 can only be completed in reset mode. The flowchart of the program is shown in Figure 4.
First, the program detects whether the CAN interface is working properly, that is, write and read to the SJA1000's test register, check if the result is consistent, if the result is consistent, enter the reset mode to initialize the setting. In the process of initialization, if the setting of a register exceeds the specified time, it is considered that the initialization failed, and the initializer automatically sends an error signal.
(2) Data transmission and reception. The SJA1000 chip has a message transmit buffer and two packet receiving buffers for CAN packets. The data is sent from the CAN controller SJA1000 to the CAN bus. First, it is automatically completed by the CAN controller, and the transmitted data program takes out the data to be transmitted in the data storage area, constitutes information frame, and blocks the ID address of the host; then Send the information frame to the send buffer of the CAN controller; finally start the send command. Information from the CAN bus to the CAN receive buffer is also automated by the CAN controller. The receiving program only needs to read the information to receive from the receive buffer and store it in the data storage area.
2.2 Implementation of RTL8019AS driver
RTL8019AS drivers, like SJA drivers, there are three functions: chip initialization, package, and bag.
(1) Initialization of RTL8019AS. The initialization process of RTL8019AS is more complicated, but it is important that it determines some important parameters in the communication process. If the register, allocation, and initialization reception and send buffer, the initialization network card receiving address, etc., which is shown in Figure 5.
Figure 5 RTL8019AS initialization flow chart
(2) Data transmission and reception. Since the physical address setting of the Ethernet has been completed in the initializer of the RTL8019AS, the transmission buffer start page address register TPSR is specified. In addition, the RTL8019AS CRC check automatic generator is also enabled, so RTL8019AS packet The sender is relatively simple. During the transmission of the packet, the AT89C55 is written to the transmit buffer of the RTL8019AS sram to be transmitted by remote DMA, and the transmission process is activated.
When receiving the packet, there are two ways of query and interrupt, given the limited processing power of the AT89C55, in the design, in this design, according to judgment Curb == Bnry + 1, it can be determined whether or not to receive a new packet, if there is The data is read from the NIC chip RAM by DMA read operation.
2.3 Gateway Protocol Conversion Process
The embedded network interface implements the interconnection of two networks. When the Ethernet application layer has data to be sent to the CAN node, the data is sent to the gateway, parsing the complete CAN protocol packet by the Ethernet controller protocol conversion module, and is sent to the CAN bus via the CAN controller. Conversely, when the CAN device has data to be sent to the user layer, first send the data to the transparent gateway, and store the complete CAN protocol data package in the buffer by the CAN controller protocol module, and then notify the main control chip, and call the Ethernet The network control protocol conversion module, encapsulates the full CAN protocol packet as the application layer data, and then sends it to the application layer of the Ethernet.
3 conclusion
Here, it is a hardware, software design, and a software design, which can be used as a module of the CAN bus node, which can be combined with an instrument and other equipment. Make it a network communication capability, compare the design of the same product, which greatly improves its priceability.
Source: Wiku Electronic Market Network
Our other product:
