introduction
The new TMS320DM365 digital media processor based on Da Vinci technology, DM365 is highly integrated, including H.264, MPEG-4, MPEG-2, MJPEG and VC1 codecs that meet the production requirements. The integrated video signal processing (ISP) solution for smart video processing functions, as well as a series of onboards, etc., the developers can reduce system cost by 25%. This article surrounds the DM365 digital media processor, the design of DM365-based embedded video acquisition and transmission system is specifically introduced.
1 Overall structure of embedded video acquisition and transmission system
This system uses current advanced WiFi wireless communication technology, combined with the H.264 video compression algorithm to construct a wireless video surveillance system. The system work process is: After the video acquisition node will be collected, the audio data, after the front-end compression, etc., convert into a unified IP packet format, transmitted to the AP in WiFi wireless mode, AP access industrial fiber Ethernet, implementation Wireless connection to existing communication networks, constitutes a sensory mining multimedia digital network. The wireless video surveillance system can be applied to the mine disaster relief emergency communication system, or it can also be used in coal mines such as underground belts, hydraulic brackets, which can greatly improve the energy efficiency of mine safety monitoring systems, saving mine production costs. The wireless video surveillance system diagram is shown in Figure 1.
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Figure 1 System overall architecture
2 system hardware implementation
2.1 System Core Architecture
The main function completed by this video acquisition and transmission system is to perform real-time smooth multimedia communication under the coal mine.
The general guiding principle of system design is to low power, low cost under the premise of maintaining real-time multimedia communication quality. Node hardware mainly includes: video capture front end, video processing module, wireless transmitting module, and power modules, and some peripheral circuits.
The principle of the system is shown in Figure 2.
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Figure 2 Camera Principle Box Chart
2.2 Video Processing Module
The video processing module uses TI's Da Vinci High Performance Multimedia Processor TMS320DM365 to complete device management, audio and video compression and transmission communication. Through external Ethernet physical layer chips, wireless network communication is implemented using the transfer WiFi chip GS1010. Support TCP / IP network protocol.
TMS320DM365 is a new digital media processor based on Davincitm Technology (Davincitm Technology) introduced by Texas Instruments (TI), a new digital media processor for portable HD video applications. The processor continues the processor architecture of DM355 in the Da Vinci family, integrated an ARM926EJ-S kernel, a H.264 HD decoding coprocessor HDVICP and an MPEG-4 / JPEG HD decoding association processor MJCP , HD video encoding of H.264 / MPEG-4 can be supported.
DM365 is integrated with video processing subsystem VPSS (Video Processing Subsystem), H.264 Coprocessor (HDVICP), ARM926EJS processor, and various peripherals, and enriched peripherals, such as high-speed USB OTG 2.0 . By combination of various expansions, DM365 can be applied to the fields of cameras, network digital cameras.
2.2.1 ARM processor
The ARM group system uses the ARMV5TEJ (32 / 16bit) instruction set ARM926EJ-S kernel CPU, which is a 32bit RSIC processor using piping pipeline with an operating frequency of 216/270 / 300MHz. The ARM CPU performs usual system control tasks, such as system initialization, configuration, power management, user interface, and user commands. ARM acts as a master and implementation of these features because it has a large program storage space and fast task handover capability, so it is more suitable for complex, multitasking and general task control.
The ARM Subsystem (ARMSS) includes ARM926EJ-S RISC processor, ARM internal memory, embedded tracking module, and embedded tracking cache module (ETM / ETM) and system control peripherals. The ARM926EJ-S RISC processor also includes a coprocessor 15, a memory management unit (MMU), 16KB instruction set, 8KB data Cache, write cache, and Java accelerator. ARM internal memory includes a 32KB internal RAM (32-bit wide access) and 16KB internal ROM. The system control ARM interrupt controller, PLL controller, power management module, and system module. Technology area
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