"TMS320DM642 is selected as the system CPU and the latest video coding standard H.264 compression algorithm is adopted to realize the wireless video monitoring and video data storage system based on CDMA network transmission.
With operators launching GRPS and CDMA1X public wireless data networks in most parts of China, video transmission through public wireless data networks has become a hot spot in research and application. It can completely solve the short-distance problem of microwave. Due to the narrow and unstable bandwidth of public wireless data network, the video compression algorithms with low coding efficiency (such as H.263, MPEG-4, etc.) are adopted, the transmission effect is not ideal, and can not meet the requirements of most monitoring occasions.
H. 264 is the latest video compression standard developed by JVT, which can be 50% lower than H.263 and MPEG-4 in the same quality. At the same time, it supports wireless network transmission, but its computational complexity is also 3-5 times that of H.263 and MPEG-4. Therefore, the general CPU system can not meet the requirements. TMS320DM642 is ti's latest high-performance digital media processor, with instructions up to 4800mips, which can meet the requirements of real-time H.264 coding algorithm.
This paper designs an embedded system based on TMS320DM642, uses H.264 video coding algorithm, and successfully develops a wireless video monitoring system based on CDMA transmission.
1 Composition of wireless video monitoring system
1.1 design requirements of wireless video monitoring system
The system requires an embedded video sending terminal to compress the collected video image in real time and send it through CDMA network. The receiving terminal uses PC to decode and display the received video data. The embedded video transmitting terminal has the following requirements:
① One PAL / NTSC standard analog video input and one analog audio input;
② CDMA access mode is adopted to send video data through the network;
③ Use CF card or hard disk to store video locally;
④ The size and frame rate of the transmitted image and the saved image are adjustable;
⑤ It can be remotely controlled through wireless network and requires low power consumption.
1.2 overall design of the system
Due to the narrow bandwidth and large bandwidth fluctuation of CDMA wireless network, H.264 is used as the video compression algorithm in the system. At the same time, local storage and CDMA transmission video are different in image size and frame rate, so two coding structures need to be used for coding respectively.
Figure 1 shows the overall structure block diagram of the system. The system mainly includes dm642cpu, video input, audio input / output, hard disk interface, serial port and USB communication (USB2.0), as well as real-time clock (RTC), display and I / O interface (LCD & I / O), SDRAM, flash and power (power) modules. The following will analyze and design each functional module in detail.
Fig. 1 system block diagram of video transmission terminal
2 hardware design of wireless video monitoring system
2.1 introduction to TMS320DM642
TMS320DM642 is a high-performance digital media processor launched by Ti for multimedia processing applications. The processor is specially tailored for the video and image market. It is especially suitable for VoIP video, video on demand (VOD), multi-channel digital video recording applications and high-quality video coding and decoding solutions.
The DSP core of tms320c64x is integrated in the DM642 processor. Under the running speed of 600MHz, the instructions can reach 4800mips. Due to its powerful computing ability, it can realize the real-time H.264 encoding and decoding algorithm.
External memory interface (EMIF) control unit is integrated in DM642, which can be directly connected with external SDRAM and flash through 20 address lines and 64 bit data bus. Because 100MHz SDRAM is adopted in this system, considering the signal integrity, SDRAM is directly connected with DM642, and flash is driven by bus and then connected.
2.2 video input module
DM642 has three video ports and supports multiple resolutions and standards, such as ccir601, itu-bt.656, bt.1120, etc. each port is 20bit wide and can be flexibly configured as one 20 / 16bit or two 10 / 8bit channels. At the same time, each port can be configured as video input or video output. In this system, VP0 is connected with SAA7113H for video input acquisition.
SAA7113H is a 9bit video decoder, which is internally composed of a two-channel analog preprocessing circuit composed of video source selection, anti aliasing filter and ADC, gain control, clock generation circuit (CGC), multi standard digital decoder, brightness saturation control circuit, etc.
It supports pal, natsc and other video input formats, and the output supports the standard itu.656yuv4 ∶ 2 ∶ 28bit format. It is controlled through I2C bus. It only needs a 24.576mhz external crystal oscillator, adopts 3.3V power supply and has power consumption less than 0.5W. See Figure 2 for the interface between SAA7113H and DM642.
Figure 2saa7113h and DM642 interface
2.3 audio input / output (codec) module
DM642 has multi-channel audio serial port (mcasp) and two multi-channel buffered serial ports (mcbsps), but they are multiplexed with video ports. Mcbsps1 in VP1 is used as the interface to connect with audio codec in this system.
Tlv320aic23b is a high-performance stereo audio codec chip launched by Ti. It has built-in headphone output amplifier, supports mic and linein input modes (one out of two), and has programmable gain adjustment for input and output.
The analog-to-digital conversion (ADCs) and digital to analog conversion (DACS) components of aic23b are highly integrated in the chip. Advanced sigma delta oversampling technology is adopted, which can provide 16bit, 20bit, 24bit and 32bit sampling in the frequency range of 8K to 96k. The output signal-to-noise ratio of ADC and DAC can reach 90dB and 100dB respectively.
Aic23b also has very low energy consumption, and the power in playback mode is only 23mW.
The interface between aic23b and DM642 is shown in Figure 3.
Figure 3 interface between aic23b and DM642
2.4 CDMA wireless transmission serial port module
The system uses q2358c serial interface module as CDMA access equipment, which supports voice communication, Chinese and English short messages, dual tone multi frequency function (DTMF) and other functions. The baud rate ranges from 300 to 115200bit / s, supports the maximum internet rate of 153kb / s, and uses at instruction set to communicate through RS-232 serial port. DM642 has no asynchronous universal serial interface, so it needs to use extended asynchronous communication chip to realize serial communication.
Tl16c752b is a UART transceiver. The maximum baud rate can reach 3MB / S (when using 48mhz clock source). It has 64BYTE transmit / receive FIFO. The start and stop of receive FIFO can be realized through software programming, and supports a variety of baud rates and serial data formats. The DM642 and its connection are controlled by EMIF. The address lines A0 ~ A2, data lines d0 ~ D7 and read-write control signal IOR / Iow are connected with the driven bus, and the strobe signal CSA / CSB is generated by gal. Tl16c752b and q2358c modules are connected through max3243 for level conversion. Figure 4 shows the connection mode of one serial interface.
Figure 4 system serial communication interface
2.5 de and USB communication module
In this system, the collected video shall be stored locally, and the data shall be saved by CF card or IDE hard disk. The data saved in CF card or de hard disk shall be read out when necessary through USB2.0. The interface between DM642 and De is controlled by the signal generated by gal16lv8.
Tusb6250 adopts USB2.0 to ATA / ATAPI bridge embedded with 8051 core. It is fully compatible with USB2.0 standard and supports eight configurable terminals (four inputs and four outputs). The internal integrated USB storage device transfer protocol is seamlessly connected with ATA / ATAPI devices.
The instruction speed of the internally integrated 60mhz8051 microprocessor can reach 30mips, 40kbyte RAM can be flexibly configured as data or code RAM, 13 general-purpose I / O ports can be used for various communication and control, and there is I2C interface. In this system, the communication between DSP and tusb6250 is realized through I2C and HPI bus. See Figure 5 for de and USB interfaces.
Figure 5dm642 interface with IDE and USB
2.6 power supply and other modules
DM642 adopts dual power supply, the core power supply is 1.4V, and the consumption current is 890ma; The I / O power supply adopts 3.3V and the consumption current is 210ma. Because the core power supply voltage is low and the current consumption is large, if LDO power supply is used, the power consumption will increase. Therefore, two switching power supply chips tps54310 are used in this system to generate 3.3V and 1.4V power supplies respectively, and the power efficiency can reach more than 90%.
DM642 provides 16 general I / OS, which can realize keyboard input, control switching value input and output. The video port VP3 of the DM642 is configured to output directly to the LCD. In addition, the system uses ds1338 as the real-time clock to provide real-time time information.
3 precautions in system design
3.1 schematic design
The internal operating frequency of DM642 is obtained by internal PLL frequency multiplication through external clock input. The PLL frequency multiplication can select x1, X6 or X12 through clkmode1 and clkmode2 pins. Therefore, the external of these two pins must be connected with corresponding resistance adjustable so that DM642 can operate at different speeds.
DM642 has a variety of boot startup modes. If flash of emifa is selected as startup, the flash chip selection must be connected to tce1. The DM642 can select the large / small mode in byte order, PCI, HPI and EMAC modes of peripherals through Landian and PCI during reset_ EN、PCI_ EEAI、HD5、MAC_ When determining the level of the EN pin, it must be considered that the level value is adjustable during reset.
The EMU [1:0] of the simulator is guaranteed to be pulled up and the trst is pulled down. In addition, when the aardy pin is not in use, ensure that it is high level, and the NMI pin is grounded when it is not in use. When selecting the HPI mode, ensure that the HPI control signal level is correct, and correctly process other unused input pins.
3.2 PCB design
As a high-performance digital media processor, DM642 not only has high internal operating frequencies of 600MHz, 720MHz and 1GHz, but also has a bus speed of 100MHz or 133MHz with the external SDRAM. If the external SDRAM fails to reach the desired speed due to wiring, the performance of the system will be reduced.
For signal buses above 100MHz, there is a signal integrity problem. To ensure the integrity of the signal, the following methods shall be adopted. The clock line of SDRAM shall be as short as possible, and the length of two SDRAMs shall be as equal as possible; Flash and other peripherals should not be directly connected to the data and address bus, but should be connected through the buffer chip (such as sn74lvt16245b); Small resistance should be connected in series on the high-speed bus, and the resistance value can be obtained through simulation. At the same time, the line is more required to be impedance limited.
There is a PLL inside the DM642. The devices connected outside the PLL should be as close to the chip as possible and must be placed on one side of the circuit board. The connection length of JTAG shall not exceed 6in. If it exceeds 6in, it shall be driven. There are both analog and digital parts in the system. Pay attention to the design of analog power supply and digital power supply to minimize the interference of digital signal to analog signal, otherwise there will be snowflakes and stripes on the collected video signal and noise from audio signal. The video and audio chips shall be powered by a separate power chip as far as possible, and the analog and digital ground shall be connected at a single point or by magnetic beads.
4 Conclusion
According to the above hardware design, the embedded wireless video monitoring system based on DM642 is completed. The system takes high-speed DSP as the core and supplemented by corresponding peripheral circuits to realize real-time H.264 video coding and decoding. At present, the system has been successfully debugged and runs stably. It provides a practical scheme for wireless video monitoring in public security, transportation, water conservancy and other industries, and has very high application value., Technology Zone
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