Explore STM32H7 chip IAP jump failure case

STM32 user feedback, he uses STM32H750VB to write user boot programs [boot code] and application [App Code]. According to the data sheet, the STM32H750 has 128K Bytes's slice, and the address is from 0x0800 0000 ~~ 0x0801 FFFF. He put the user bootloader in the 0x0800 0000 ~ 0x0800 2FFF, the application placed in 0x08003000 ~ 0x0801 FFFF. However, when he is designing such a storage allocation, it is always impossible to achieve jump from the Boot area to the App area. Based on the user's feedback, give him some reminders, such as interrupt vector table positioning issues, customers say that they have noticed, the code should have no problem. I found a verification test on the question of the Batch STM32H743 on the question. It is found that the jump from the boot area to the App area is not abnormal, then what is the problem with the customer? The feedback information of the customer email again again. He used the default internal SRAM area for AXI SRAM, address interval in 0x24000000 --0x2407fff, the A area in the table below, and the default internal SRAM area I used is DTCM SRAM, address interval in 0x20000000 -0x2001fffff, that is, the table B zone. Is this difference result in different results of jump? Of course, these two SRAM districts still have differences in use. I tried to test the default SRAM area of the test project from TCM RAM to AXI SRAM for testing. It is really impossible to achieve jump from the boot area to the App area! It seems that jump failure is related to this default SRAM area. That is to say, when I use the DTCM RAM by default, the jump is normal if I use the AXI SRAM by default. We know that the STM32H7 series chip supports D-Cache / I-Cache. Specifically, if you use AXI SRAM to use D-Cache. The D-Cache has also been opened in our engineering code, and if it is for this reason, it should be able to achieve normal jumps if you close the D-Cache before doing a jump operation. So the code is slightly adjusted, in fact, the code is added to the D-Cache code. [Red box] Test again, at this time, even if the AXI RAM is used as the default memory space, it can also be reliably jumped from the User Boot area to the App area, perfect implementation. Here, the access characteristics of the STM32H7 series chip are involved in the access characteristics of different storage regions and D-Cache related knowledge, and there are quite a lot. If you are interested, you can view the relevant technical manual to make further understanding and exploration. Have time, follow-up will be further communicated here. At this point, you share the application case, one by making an app, two doing the brick introduction jade. , Read the full article, original title: a case of a STM32H7 chip IAP jump failure Article Source: [Micro Signal: STMCU832, WeChat Public Number: Tea MCU] Welcome to add attention! Please indicate the source of the article.