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    FIR filter design based on matlab FPGA verilog

     

    This routine implements the 8th-order filter, 9 coefficients, because of the symmetry of the coefficient, h (0) = h (8), H1 (1) = h (7), h (2) = h (6), h (3) = h (5), H (4) is a single coefficient in the middle. According to the formula: Realization diagram: Derived when the coefficient N is an even number, e.g. N = 4: y (n) = h (0) * {x (0) + x (n-3)} + h (1) * {x (n-1) + x (n-2)} When the coefficient N is odd, for example, N = 5: y (n) = h (0) * {x (0) + x (n-1)} + h (1) * {x (n-1) + x (n-3)} + h (2) * x (n-2) 1, with the quantized filter coefficients and generating matlab After setting the parameters, click "Design Filter" button, "file" - "export", the filter coefficient deriving the Workspace, as shown below: Run: Num = Num ', the filter coefficients are copied to the file COFFICIENT.dat. Quantized coefficients: run in matlab quantization.m 2. Description Generating a sine wave with a matlab program table sin_1MHz_gen.m, change the variable f0 = 1.5e6 may generate waveforms at different frequencies. The number of data of the waveform data stored in the first cycle signal_1m.dat file is stored Fs / Fo molecular ratio of the smallest positive integer, such as Fs = 25MHz, Fo = 0.3MHz, Fs / Fo = 250 / 3 (Fs = 25 / 24MHz), the number of data stored in the waveform for the beginning of the file signal_1m.dat 250 data. Signal_gen0.v respective statements if (i0<50) corresponding to if (i0<250). signal_1m.dat placed under simulation simulation directory 3, the filter multisim simulation Run matlab, produced by sin_1MHz_gen.m 5MHz (f0 = 5e6) sinusoidal signal, Fs / Fo = 5, the first five data hex_sin_data signal_1m.dat data file stored, if the statement of the respective signal_gen0.v (i0 <50) corresponding to if (i0<5). FIG following simulation waveform (input and output signals of fir filter): Run matlab, produced by sin_1MHz_gen.m 1MHz (f0 = 1e6) sinusoidal signal, Fs / Fo = 25, the data hex_sin_data first five data files stored signal_1m.dat, if the statement of the respective signal_gen0.v (i0 <5) corresponding to if (i0<25). FIG following simulation waveform (input and output signals of fir filter): This shows that the attenuation functions of FIR band signals. Part of the code: // Date: 2012-5-27 // Description: 8-order FIR filter, 2MH passband, stopband 8MHz, band attenuation 80dB, 1dB passband // Uesedfor // Taobao: // E-mail: [email protected] // ================================================ ========================== timescale 1 ns / 1 ns module fir_filter ( i_fpga_clk, i_rst_n, i_filter_in, o_filter_out ); input i_fpga_clk; // 25MHz input i_rst_n input signed [7: 0] i_filter_in; // data rate 25Mh output reg signed [7: 0] o_filter_out; // filtered output // ================================================ ============== Order filter coefficients // 8 of 9 coefficients, coefficient symmetry // ================================================ ============== wire signed [15: 0] coeff1 = 16'd239; wire signed [15: 0] coeff2 = 16'd1507; wire signed [15: 0] coeff3 = 16'd4397; wire signed [15: 0] coeff4 = 16'd7880; wire signed [15: 0] coeff5 = 16'd9493; // ================================================ =============== // delay chains // ================================================ =============== reg signed [7: 0] delay_pipeline1; reg signed [7: 0] delay_pipeline2; reg signed [7: 0] delay_pipeline3; reg signed [7: 0] delay_pipeline4; reg signed [7: 0] delay_pipeline5; reg signed [7: 0] delay_pipeline6; reg signed [7: 0] delay_pipeline7; reg signed [7: 0] delay_pipeline8; always @ (posedge i_fpga_clk or negedge i_rst_n) if (! i_rst_n) begin . Delay_pipeline1 .1881 = 8'b0; . Delay_pipeline2 .1881 = 8'b0; . Delay_pipeline3 .1881 = 8'b0; . Delay_pipeline4 .1881 = 8'b0; . Delay_pipeline5 .1881 = 8'b0; . Delay_pipeline6 .1881 = 8'b0; . Delay_pipeline7 .1881 = 8'b0; . Delay_pipeline8 .1881 = 8'b0; end Else begin delay_pipeline1 < = i_filter_in, Read more

     

     

     

     

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