Changed the program for several days. I don't know what to say. Go directly to the code/****************************************************//****************************************************/ /* made by Jerry *//****************************************************//****************************************************/` TImescale 1ns/1nsmodule happy( Clk, Rst_ n, SCLK, DIN, FSY);// Huang Zheng input Clk; // System input clock input Rst_ n; // Reset signal output reg DIN; // AD9833 input data output reg FSY; // Data input control signal output reg SCLK; // Serial communication clock/* Serial communication: three wire SPI (serial peripheral interface) is adopted Several important serial interface descriptions SCLK: serial clock input, data input AD9833 at the falling edge of the clock Din: serial data input interface, the number of input data bits is 16bit Fsync: active low control input. This is the frame synchronization signal for the input data. When fsync is taken low, the internal logic is informed that a new word is being loaded into the device. Data can be input to the chip only when fsync is low After the 16th falling edge of SCLK, fsync is pulled up*/ wire trans_ done; // 2 byte data transmission completion flag signal reg[3:0]cishu; // Word communication times register, which is used to control the transmission process reg[3:0]DIV_ CNT; // Frequency division counter for sequence machine control reg SCLK2X; // 2X SCLK sampling clock reg [8:0]SCLK_ GEN_ CNT;// SCLK generation and sequencer counter reg en;// Conversion enable signal parameter DIV_ PARAM=2; parameter DAC_ data0=16'h2100, // 0010_ 0001_ 0000_ 0000 DB13 = 1 means to write the complete frequency control word twice and reset the register to DAC at the same time_ data1=16'h69f1, // six thousand eight hundred and eighty-six // 0110_ 1001_ 1111_ 0001: low 14bit is the input frequency data, DB15: db14 = 01 indicates the selection frequency register feg0dac_ data2=16'h4000, // 0100_ 0000_ 0000_ 0000 high 14bit = 0dac_ data3=16'hc000, //1100_ 0000_ 0000_ 0000: select phase register 0, data = 0 DAC_ data4=16'h0100, // 0000_ 0001_ 0000_ 0000DAC_ data5=16'h2100, // Select data write once, DB13 & rest = 1dac_ data6=16'h2000, // Set the phase register 0 as the phase accumulator DAC_ data7=16'h2000; // Select sine wave // Data transmission enable control module always@(posedge Clk or negedge Rst_ n)if(! Rst_ n)en <=# 1 1'b1; else if(trans_ done)en <=# 1 1'b0; elseen <= en; // Complete data transmission completion flag signal assign trans_ done = (cishu ==4'd8 ) && SCLK2X; // Generate 2x SCLK clock counter always@(posedge Clk or negedge Rst_ n)if(! Rst_ n)DIV_ CNT <= # one 4'd0; else if(en)beginif(DIV_ CNT == (DIV_ PARAM - 1'b1))DIV_ CNT <= # one 4'd0; else DIV_ CNT <= # one DIV_ CNT + 1'b1; end elseDIV_ CNT <= # one 4'd0; // Generate 2x SCLK clock counter The result is that the SCLK period is 40ns perfect always @ (posedge CLK or negedge RST_ n)if(! Rst_ n)SCLK2X <= # one 1'b0; else if(en && (DIV_ CNT == (DIV_ PARAM - 1'b1)))SCLK2X <= # one 1'b1; elseSCLK2X <= # one 1'b0; // Generate sequence counter always @ (posedge CLK or negedge RST)_ n)if(! Rst_ n)SCLK_ GEN_ CNT <= # one 9'd0; else if(SCLK2X && en)begin if(SCLK_ GEN_ CNT == 9'd271)SCLK_ GEN_ CNT <= # one 9'd271; elseSCLK_ GEN_ CNT <= # one SCLK_ GEN_ CNT + 1'b1; endelseSCLK_ GEN_ CNT <= # one SCLK_ GEN_ CNT; /* ******************* Move the data out of the chip in turn*********************/ always@(posedge Clk or negedge Rst_ n) if(! Rst_ n) begin DIN <=# 0 1'b1; SCLK <=# one 1'b1; FSY <=1'b1; cishu<=4'd0; end else if((! trans_ done)&&SCLK2X) begin case(SCLK_ GEN_ CNT)/******************************************************/ /* Transmission DAC_ data0*/ /******************************************************/ 0:begin DIN <= # 1 DAC_ data0[15]; FSY<=1'b0; SCLK <= # five 1'b0; end 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29: begin SCLK <= # one 1'b1; end 31: begin SCLK <= # one 1'b1; FSY<= 1'b1; end 2: begin DIN <= # 1 DAC_ data0[14]; SCLK <= # 1 1'b0; end 4: begin DIN <= # 1 DAC_ data0[13]; SCLK <= # 1 1'b0; end 6: begin DIN <= # 1 DAC_ data0[12]; SCLK <= # 1 1'b0; end 8: begin DIN <= # 1 DAC_ data0[11]; SCLK <= # 1 1'b0; end 10: begin DIN <= # 1 DAC_ data0[10]; SCLK <= # 1 1'b0; end 12: begin DIN <= # 1 DAC_ data0[9]; SCLK <= # 1 1'b0; end 14: begin DIN <= # 1 DAC_ data0[8]; SCLK <= # 1 1'b0; end 16: begin DIN <= # 1 DAC_ data0[7]; SCLK <= # 1 1'b0; end 18: begin DIN <= # 1 DAC_ data0[6]; SCLK <= # 1 1'b0; end 20: begin DIN <= # 1 DAC_ data0[5]; SCLK <= # 1 1'b0; end 22: begin DIN <= # 1 DAC_ data0[4]; SCLK <= # 1 1'b0; end 24: begin DIN <= # 1 DAC_ data0[3]; SCLK <= # 1 1'b0; end 26: begin DIN <= # 1 DAC_ data0[2]; SCLK <= # 1 1'b0; end 28: begin DIN <= # 1 DAC_ data0[1]; SCLK <= # 1 1'b0; end 30: begin DIN <= # 1 DAC_ data0[0]; SCLK <= # 1 1'b0; end 32: begin SCLK <= # 1 1'b0; end 33: begin SCLK<=1'b1; cishu<=4'd1; end /********************************************************/ /* Transmission DAC_ data1*/ /********************************************************/ 34: begin DIN <= # 1 DAC_ data1[15]; FSY<=1'b0; SCLK <= # five 1'b0; end 35,37,39,41,43,45,47,49,51,53,55,57,59,61,63: beginSCLK <= # one 1'b1; end65:beginSCLK <= # one 1'b1; FSY<=#1 1'b1; end 36: begin DIN <= # 1 DAC_ data1[14]; SCLK <= # 1 1'b0; end38: begin DIN <= # 1 DAC_ data1[13]; SCLK <= # 1 1'b0; end40: begin DIN <= # 1 DAC_ data1[12]; SCLK <= # 1 1'b0; end42: begin DIN <= # 1 DAC_ data1[11]; SCLK <= # 1 1'b0; end44: begin DIN <= # 1 DAC_ data1[10]; SCLK <= # 1 1'b0; end46: begin DIN <= # 1 DAC_ data1[9]; SCLK <= # 1 1'b0; end48: begin DIN <= # 1 DAC_ data1[8]; SCLK <= # 1 1'b0; end50: begin DIN <= # 1 DAC_ data1[7]; SCLK <= # 1 1'b0; end52: begin DIN <= # 1 DAC_ data1[6]; SCLK <= # 1 1'b0; end54: begin DIN <= # 1 DAC_ data1[5]; SCLK <= # 1 1'b0; end56: begin DIN <= # 1 DAC_ data1[4]; SCLK <= # 1 1'b0; end58: begin DIN <= # 1 DAC_ data1[3]; SCLK <= # 1 1'b0;
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