Design background: DS1302 is a real-time clock circuit with high performance, low power consumption and ram launched by Dallas company in the United States. It can time year, month, day, week, hour, minute and second. It has leap year compensation function and working voltage is 2.5V ~ 5.5V. Three wire interface is used for synchronous communication with CPU, and burst mode can be used to transmit multiple bytes of clock signal or RAM data at one time. The DS1302 has an internal 31 × 8 ram register for temporary storage of data. Design principle: the package of DS1302 chip is as follows: it has 8 pins. In our design, we only need to drive 3 pins. The other pins are connected with our hardware and FPGA. Sometimes clock first SCLK, serial data interface IO, and CE. Its working principle is to first pull CE high in the process of data transmission, write data on the rising edge of each data, input data on the falling edge, and only read and write one bit of data at a time. Initially, we choose to read and write through an 8-bit control instruction. If the control instruction is in single byte mode, the rising edge of 8 consecutive pulses is written, and the falling edge reads data, only one byte can be read at a time. If it is in burst mode, the 7-byte time register can also be written through continuous pulses at one time, and the 8-328-bit RAM data can be read at one time. The control instruction has 8 bits, and the seventh bit must be high. If it is 0, writing is prohibited, the sixth bit 0 is the read-write operation of the clock register, and if it is 1, it controls the read-write operation of the RAM area. Bit1 -- 5 is the operation of related registers, and bit0 is the read-write operation. The setting of each register and the representation of each are shown in the figure below. In the figure, the number of control words and the address of the write register when we read and write at high speed, and the time of 8 bits written indicate that we can set an initial time through the table below. The trickle register mainly determines the charging characteristics of DS1302. The trickle charging selection bits are 4-7 bits, 1010 trickle charging and other prohibited charging, the diode selection bits are 3-2 bits, and the resistance selection bits are 1-0 bits. The specific choices are as follows: in burst mode, it means that we can write continuously and read continuously. When writing continuously, seven clock registers must be filled. The sequence diagram is as follows, which is SPI communication. The following table shows the data delay, clock cycle and other times in the process of data transmission. This design realizes the monitoring of real-time clock by configuring DS1302 chip. We select the time we want to display on the nixie tube by controlling two keys. Press key 1 to display the day of the week, press key 2 to display the year, month and day, not the time, minute and second. In this way, we display the display of our digital meter. My idea is to first turn on the write protection, write in registers one by one, then turn off the write protection, and then read out the data. Design architecture diagram: Design Code: top-level module 0modules_ 1302(clk,rst_ n,sclk,ce,data,sel ,seg7,key); 12 inputclk,rst_ n; 3 wire[23:0]shi_ fen_ miao; 4 wire[23:0]nian_ yue_ ri; 5 wire[23:0]day; 6 outputsclk,ce; 7 inoutdata; 8 output[7:0]seg7; 9 output[5:0]sel; 10 input[1:0]key; 11 12 seg seg_ dut(13 .clk(clk),14 .rst_ n(rst_ n),15 .sel(sel),16 .seg7(seg7),17 .data_ in(shi_ fen_ miao)18 ); 19 20 time_ ce time_ ce(21 .clk(clk),22 .rst_ n(rst_ n),23 .data(data),24 .sclk(sclk),25 .show_ data(shi_ fen_ miao),26 .ce(ce),27 .key(key)28 ); 29 30 endmodule design module 0moduletime_ ce(clk,rst_ n,data,sclk,show_ data,ce,key); 12 inputclk,rst_ n; 3 inoutdata; 4 outputregsclk; 5 outputregce; 6 input[1:0]key; 7 8 regbuff; 9 regflag; 10 reg[7:0]times; 11 outputreg[23:0]show_ data; 12 reg[23:0]shi_ fen_ miao; 13 reg[23:0]nian_ yue_ ri; 14 reg[7:0]day; 15 16 17 assigndata =flag ? buff :1'bz;// Define a three state to control the input and output 18 19 parameterw of the IO port_ 1302 =16'h8e00; // Write unprotected 20 parameterw_ miao =16'h8030; // 30 seconds 21 parameterw_ fen =16'h8211;// 11 points 22 parameterw_ shi =16'h8408; // 8:23 parameterw in 24-hour system_ ri =16'h8621; // 21-24 parameterw_ yue =16'h8803; // March 25 parameterw_ nian =16'h8c17; // 2017 26 parameterw_ day =16'h8a03; // Week 327 parameterrr_ 1302 =16'h8e80;// Write protect toner 28 parameterw_ dian =16'h90a7;// Two diodes 829 30 / / read register settings 31 parameterr_ miao =8'h81; 32 parameterr_ fen =8'h83; 33 parameterr_ shi =8'h85; 34 parameterr_ ri =8'h87; 35 parameterr_ yue =8'h89; 36 parameterr_ nian =8'h8d; 37 parameterr_ day =8'h8b; 38 39 reg[14:0]count; 40 reg[15:0]reg_ data; 41 regw_ flag; 42 regr_ flag; 43 reg[1:0]state_ r; 44 45 / / define a sequence and to control the timing of reading and writing 46 always @ (posedgeclk) 47 If (! rst_ n)48 begin49 count <=0; 50 state_ r <=0; 51 end52 else53 case(state_ r)54 0 : if(r_ flag ||w_ flag)55 state_ r <=1; 56 else57 state_ r <=0; 58 1 : if(count <(400+34*250))59 count <=count +1; 60 else61 begin62 state_ r <=0; 63 count <=0; 64 end65 default:state_ r <=0; 66 endcase67 68 / / start with CE low, and then pull it high. After a minimum of 4us, pull sclk69 high. / / when writing, we control the bus, write the command, and release bus 70 when reading. / / when writing data on the rising edge, we need to prepare data before the rising edge, and 71 / / when reading data on the falling edge, we need to receive data after the falling edge 72 reg [7:0] time_ temp; 73 always@(posedgeclk)74 if(! rst_ n)75 begin76 sclk <=0; 77 ce <=0; 78 flag <=0; 79 times <=0; 80 buff <=0; 81 time_ temp <=0; 82 end 83 else84 case(count)85 20 : begince <=1; flag <=1; end86 400+1*250 : beginsclk <=0; buff <=reg_ data[8]; end87 400+2*250 : beginsclk <=1; end88 400+3*250 : beginsclk <=0; buff <=reg_ data[9]; end89 400+4*250 : beginsclk <=1; end90 400+5*250 : beginsclk <=0; buff <=reg_ data[10]; end91 400+6*250 : beginsclk <=1; end92 400+7*250 : beginsclk <=0; buff <=reg_ data[11]; end93 400+8*250 : beginsclk <=1; end94 400+9*250 : beginsclk <=0; buff <=reg_ data[12]; end95 400+10*250 : beginsclk <=1; end96 400+11*250 : beginsclk <=0; buff <=reg_ data[13]; end97 400+12*250 : beginsclk <=1; end98 400+13*250 : beginsclk <=0; buff <=reg_ data[14]; end99 400+14*250 : beginsclk <=1; end 100 400+15*250 : beginsclk <=0; buff <=reg_ data[15]; end 101 102 400+16*250 : if(w_ flag)103 sclk <=1; 104 elseif(r_ flag)105 beginsclk <=1; end106107 400+17*250 : if(w_ flag)108 beginsclk <=0; buff <=reg_ data[0]; end109 elseif(r_ flag)110 beginsclk <=0; flag <=0; end111 112 400+18*250 : if(w_ flag)113 sclk <=1; 114 elseif(r_ flag)115 beginsclk <=1; times[0]<=data; end116117 400+19*250 : if(w_ flag)118 beginsclk <=0; buff <=reg_ data[1]; end119 elseif(r_ flag)120 sclk <=0; 121 122 400+20*250 : if(w_ flag)123 sclk <=1; 124 elseif(r_ flag)125 beginsclk <=1; times[1]<=data; end126127128 400+21*250 : if(w_ flag)129 beginsclk <=0; buff <=reg_ data[2]; end130 elseif(r_ flag)131 sclk <=0; 132 133 400+22*250 : if(w_ flag)134 sclk <=1; 135 elseif(r_ flag)136 beginsclk <=1; times[2]<=data; end137138 400+23*250 : if(w_ flag)139 beginsclk <=0; buff <=reg_ data[3]; end140 elseif(r_ flag)141 sclk <=0; 142 143 400+24*250 : if(w_ flag)144 sclk <=1; 145 elseif(r_ flag)146 beginsclk <=1; times[3]<=data; end147148 400+25*250 : if(w_ flag)149 beginsclk <=0; buff <=reg_ data[4]; end150 elseif(r_ flag)151 sclk <=0; 152 153 400+26*250 : if(w_ flag)154 sclk <=1; 155 elseif(r_ flag)156 beginsclk <=1; times[4]<=data; end157158
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