"Introduction
H. The high coding efficiency of 264 is at the cost of its high complexity, which restricts its application in high resolution, real-time processing and so on. FPGA device adopts pipeline control strategy and parallel processing mode, which can provide hardware acceleration engine for H.264 complex coding module. The transform quantization module is frequently called in the H.264 coding algorithm. Therefore, on the premise of reasonably controlling its resource consumption, it is of great practical significance to improve the working frequency and data throughput of the transform quantization module, and complete the transform quantization structure with a series of complete functions, which has also become the primary problem of the current research. H. 264. The transform is based on DCT, which all adopts integer DCT transform, so as to avoid the mismatch between forward transform and inverse transform, not only do not lose decoding accuracy, but also suitable for FPGA hardware implementation.
1 algorithm principle and analysis
1.1 transform algorithm and analysis
H. 264 transform is an integer DCT transform. The algorithm realizes the zero matching between the inverse transform at the encoder and decoder, so as to reduce the loss of decoding accuracy. Usually, H.264 transform coding is 4 × In units of 4 blocks, the core transformation matrix is as follows:
When a = 1 in the core transformation matrix, it is the DCT forward transformation matrix CF,; If all 2 in DCT forward transformation matrix CF is changed to 1 and all symbols remain unchanged, it becomes Hadamard transformation matrix hi; If all 2 in the above matrix is changed to 1 and a = 1 / 2, and all symbols remain unchanged, it is the DCT inverse transformation matrix CTI.
1.2 quantization algorithm and analysis
H. The hierarchical scalar quantizer of 264 supports up to 52 quantization steps qstep, which is indexed by the quantization parameter QP. A wide range of quantization steps can flexibly and accurately control the balance between bit rate and quality.
In the integer algorithm, the quantization process can be realized by the following operations:
Where: W is residual coefficient Indicates binary shift right; The intra block and inter block f are 2qbits / 3 and 2qbits / 6 respectively; MF is a multiplication factor whose value can be obtained by looking up the multiplication factor table according to different positions of W (I, J) in the matrix and different quantization parameters QP.
The inverse quantization method of coefficient Z is as follows:
Where: the scale factor V can be obtained by looking up the scale factor table according to the different positions of Z (I, J) in the matrix and the different quantization parameters QP.
2 FPGA hardware design and Implementation
2.1 overall structure of transform quantization hardware
In the H.264 encoder, the residual data obtained after prediction is divided into two channels after transformation T and quantization Q: one channel is used for entropy coding after reordering recoder; The other is the reconstruction path. After inverse quantization Q-1 and inverse transformation T-1, it is added with the prediction value p to obtain the reconstruction value, which is used for the prediction coding of the subsequent macroblock.
H. In the 264 coding standard, in the intra prediction mode, 16 × 16 macroblocks (luminance components) × Four blocks are transformed by DCT, and then DC coefficients are extracted to form a 4 × 4 DC blocks; For this 4 × 4. The DC block shall be subject to Hadamard transform first, and then quantized. Note in the Reconstruction Path: for 4 × 4 DC block, the inverse Hadamard transform shall be carried out first, and then the inverse quantization shall be carried out in order to maximize the dynamic range of the inverse transform; Then according to this 4 × The 16 values in the 4 DC block are the inverse quantized 16 × 16 macroblocks for inverse DCT transformation. The same is true for the DC coefficient of chroma component, which needs to be further transformed. H. The overall structure of 264 transform quantization is mainly divided into four modules, and its block diagram is shown in Figure 1.
DC in structure block diagram_ Reg is a set of registers used to store all DC coefficient values. Two synchronous FIFOs are used to store the inverse quantized AC coefficients. After the inverse transformation and inverse quantization of DC coefficients are completed, they are sent to the final inverse DCT transformation module for processing. Two synchronous FIFOs write successively under the clock control, and one of them stores 4 × Two lines of data output by 4 blocks of inverse quantization, and the other stores this 4 in the next clock × The other two lines of data output by 4 blocks of inverse quantization. When reading, read two FIFOs at the same time, that is, this 4 in one clock × All 16 values after inverse quantization of 4 blocks appear at the input of the inverse transform module at the same time.
2.2 transform module (DCT / Hadamard transform) and inverse transform module
(IDCT / ihadamard inverse transformation) the design can be derived from the DCT transformation matrix:
Similarly, Y01 ~ Y03 and Y20 ~ Y23 can also be obtained by expanding equation (5). Similarly:
From the analysis of the above transformation algorithm, it can be seen that the core transformation matrix of Hadamard transformation and DCT transformation only has the difference of whether to multiply by 2. Therefore, Cr in equations (5) and (7) is replaced by Hi, and 2 becomes 1, so Hadamard transformation can be obtained.
In the actual hardware circuit, the operations of multiplying by 2 and dividing by 2 can be realized by shift. In addition, DCT forward transform and Hadamard transform do not operate simultaneously in the whole transformation process. Therefore, DCT forward transform and Hadamard transform are combined and time-sharing multiplexed to distinguish which transformation is currently multiplied by 2. At the same time, 16 residual data are input at the same time, 8-bit transformation data are output, and one 4-bit is output every 2 clocks × Transformation results of 4 blocks. This not only makes full use of hardware resources, but also can process a 4 at one time × All 16 data of 4 residual blocks ensure efficiency. The core transformation of DCT transformation and Hadamard transformation can be realized by fast butterfly algorithm, as shown in Figure 2.
The core transform of IDCT inverse transform and ihadamard inverse transform is analyzed, and the principle is similar to the above.
2.3 quantization and inverse quantization module design
The whole quantization and inverse quantization module is realized by multiplier, adder and shift operation, and two ROMs in FPGA are used to store the multiplication factor MF and scale factor V of forward and inverse quantization respectively.
Since the output of the conversion module is 8 bits, the quantization module adopts 8 data inputs and outputs 4 bits every 2 clocks × Quantization results of 4 blocks. The inverse quantization module also adopts 8 data inputs, and outputs one 4 every 2 clocks × Inverse quantization results of 4 blocks.
3 timing analysis and hardware debugging verification
The structural design is programmed in VHDL and integrated with XST in ISE environment, and the integrated frequency reaches 112 MHz. The FPGA used in the design is xc2v1500 produced by Xilinx company, and the online logic analyzer chipscope is used to observe the quantized output data (Quant)_ out_ i) And inverse transformed residual output data (INV_ dct_ i）； Figure 3 shows the residual output data (INV) after inverse transformation_ dct_ i）。 The input data adopts 4 with the same value × 4 blocks, so the output data is exactly the same. Waveform display: output 8 data each time; For 16 brightness 4 of a macroblock × When processing 4 blocks, transform quantization (including AC / DC) can be completed in 45 clocks for coding, transform quantization and inverse transform inverse quantization can be completed in 91 clocks to obtain the residual for reconstruction, and the whole process of reconstructing the residual data of a macroblock from input to inverse transform output can be completed in 236 clocks.
4 Conclusion
The proposed H.264 transform quantization structure is completely implemented based on FPGA. Each clock outputs 8 data, and every 2 clocks get 4 pairs × The final result of 4 block processing. On the one hand, pipeline operation is adopted to process 16 data in parallel, which improves the data processing speed. On the other hand, time-sharing multiplexing technology saves hardware resources to a certain extent. Compared with only some functions in the literature, this paper realizes a series of complete operations to obtain the residual value for reconstruction from the residual input through transform quantization and inverse transform inverse quantization, and ensures the optimal processing of resources at a certain data processing speed, which is suitable for hardware acceleration of H.264 encoder., Read the full text“
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