H.264 is a new video compression standard for ITU-T VCEG organization and ISO / IEC MPEG organization, compared to other video compression algorithms, the compression ratio is high, and the algorithm is complicated. Due to the complexity of the encoding algorithm, the system is very strict, and therefore, the design of the H.264 decoded special chip is used when designing the decoder. For a large design project, it is generally used by a top-down design method to divide each function module into a child module. The video controller module is the data interface of the chip and the display platform, and it is necessary to divide it into a sub-module separately. In order to improve the success rate of the design, FPGA-based prototype verification is used in the initial stage of the design. The FPGA prototype verification platform of the entire system is shown in Figure 1, the platform is divided into two parts, hardware design, and the RISC CPU-based software decoding. Two part of collaborative work, can verify software and hardware decoding results, but accelerate the entire decoding Process.
Figure 1 H.264 Decoding chip FPGA prototype verification platform
Figure 2 Output Video Control Module Structure Box Diagram
Design and implementation of video control modules
Video Control Module Principle Box and Function Analysis
The structure block diagram of the output video control module is shown in Figure 2, which has 2 clock domains: the system clock domain and the display clock domain. The system clock frequency uses a fixed 166MHz according to the selected SDRAM type; for HD TV with a resolution of 1280 × 720, the display clock field can be selected from 70 MHz.
The system clock field contains two external interfaces: the system interface, which mainly includes instructions issued by the upper system and the feedback information of the output control module; the DRAM interface, the signal containing the data dedicated bus is provided by the output control module, which is used to request the DRAM request Image data.
The display input control sub-module (DISP IN CTRL) in the system clock domain is first used to receive the STARTDISP and EndDisp signals from the system to initiate or turn off the output display function of the video data, and simultaneously send a frame image display signal (Framedone). The notification system replaces the address information of the next pair image; second, it is used to send a request to the DRAM, read the image data you need to display by the dedicated data channel; it also controls the input multiplex module (INPUT MUX), Thus, the task of writing data in the slices; Finally, the module interacts with the information interaction of the display clock domain, sending a display enable signal (CLK DOMAIN SYNC) to control the opening of the image display and closure. Another sub-module of the system clock domain - The input multiplex module selects the in-slice double-port SRAM, controls the memory address, and completes the task to display the image data to the memory.
The display clock field contains an external display device interface, which mainly includes a control signal for display and data information that has been converted. The display clock domain contains two sub-modules, one is the output multi-channel selection submodule (OUTPUT MUX) for implementing the selection and address control of the double-port SRAM, reading the image data to be displayed in accordance with certain laws; Package. Another sub-module is a display output control module (DISP OUT CTRL) for implementing the control of the TV encoder, the conversion of the YUV signal to the RGB signal, and the zoom of the digital image, including the display clock, row synchronization, frame synchronization, and RGB image data, etc .; it also controls the output multiplex module to read display data; Finally, it interacts with the system clock domain, and cooperates with the transfer between two clock domains.
Special technology adopted by the video control module
The clock domain synchronization module is the focus of the output control module design, which is mainly responsible for the control signal transfer between the two clock domains. Signal delivery design across the clock domain is more troublesome, so the signal transmitted is divided into two categories: data signals and control signals, where the control signal is passed through the clock domain synchronization module. The number of signals that need to be transmitted across the clock domain will be streamlined. Only 2 signals are required in the final scheme: Wrdone signal is issued by the system clock domain, notifying that the data in a block of double-port SRAM in the clock domain has been updated, you can read and read and Make display output; the RDDONE signal is issued by the display clock domain, and the data in which the data of a block SRAM in the system clock domain has been displayed, and the internal data can be updated. The signal is transmitted between different clock domains to take actions to eliminate metastability (Metastability), which allows the signal to lathe output through the two-stage register, as shown in FIG.
Figure 3 Inter-clock domain signal metastable elimination circuit
Figure 4 Hardware implementation block diagram of the video output sub-module
There are two points in the design, first, first, the clock domain synchronization circuit should be placed in a separate module to ensure the optimization of the integrated tool, the correctness of timing analysis, and convenient circuit analysis and commissioning; at the same time, in order to enable the target of the signal The clock domain is collected to signal changes, and the control signals transmitted in the design use level signal characterization.
Another signal to be transmitted between the clock domain is a data signal, since the number of data signals is large, and the variation is faster, so their transmission is implemented by double DPRAM. Double DPRAM requires the read and write port to meet the operation of the same storage address, otherwise the data transfer error will occur, and even the hardware circuit is destroyed. Therefore, in order to avoid the read and write conflict of DPRAM, the "Ping Pong" buffer method is designed. Two DPRAMs alternately access the decoded brightness or color difference data: When the display portion reads data in a DPRAM, the system Write next to another DPRAM to display the data, two DPRAMs are exchanged when the data is read. This part is shared with 4 DPRAMs, and 2 blocks pass the brightness signal, and the color difference signal is transmitted.
The following analysis is implemented in the video controller to display the format conversion algorithm used to the output sub-module, the image zoom processing algorithm, and their hardware implementation.
Display data format conversion analysis
According to the SIL 164 DVI signal encoding chip data, reference to the YUV → RGB conversion format given in the H.264 video coding standard, the fixed conversion algorithm used in the design is shown in the following formula:
The above equation is fixed, and the transition is achieved using shift and adding, as shown in the following formula:
YUV in the hardware design, RGB signals are represented by 8-bit unsigned numbers, and the intermediate variable uses 12-bit guarantee accuracy. Finally, the calculated RGB results are taken within 0 "255", the power index and division operation in the formula are implemented by shift.
Algorithm Analysis of Digital Image Zoom
For an original image of a resolution of M × N, all YUV values of all the sample points can be represented by the M × N-order matrix:
The pixel points are represented by f (m, n), where 0 ≤ m ≤ m, 0 ≤ n. Scaling a digital image, which is a heavy sample for a digital image. It is assumed that the zoom multiple of the raw digital image is high and wide is S1 and S2, respectively, according to the law of Nyquist sampling, should be used New horizontal and vertical sampling cycle 740) this.width = 740 "Border =" undefined "> Sampling the original digital image. Get zoomed digital image F '(M', N '):
It can be seen from the above formula that each of the reconstructed pixels f '(m', n ') in the scaled digital image is the weighting and sum of the various pixels of the original digital image. If the hardware design is used directly, the amount of calculation will be very large. In order to simplify design difficulty, saving chip costs, can be simplified on the basis of impact on image quality. The image pixel value after the reconstruction depends primarily on the value of the two sampling functions. In practice only
The value equal to 1, that is, the point satisfied. Further simplification, it can be taken, indicating that the logarithm is rounded, and the simplified expression: f '(m', n ') = f (m, n) is obtained.
Digital image format conversion and scaling hardware implementation
When designing this project, the display device uses a high-definition TV that is 1280 × 720, and outputs the image center alignment when outputting to a high-definition TV display. When the decoded digital image data is delivered to a high definition TV display, if the image zoom processing is not passed, the digital image of the display screen is displayed, and the other places are filled with black. Follow the above laws when scaling. First, the front end of the video controller output module is converted according to the data of the progressive scan, and then the RGB is not zero (i.e., the black) pixel data is placed in each frame and the progressive scan rules. In the same size, the block is buffered, as shown in Figure 4.
The working mode is the same as the previous DPRAM, and after reading the address of the data in RAM1 or RAM2, the row of the point pixel value can be obtained by the address decoder, i.e., the value of M, N is obtained. The M, N value is sent to the image scaling processing unit, and the new image data and the new image data address are obtained by the zoom processing, and then the address decoder is obtained in the output RAM3 in the output RAM 3, the address is obtained. Data used to store formats. Finally, the RGB data required to display the display is directly output from the RAM 3 of the storage conversion data.
Conclusion
After the design is complete, this video controller module is integrated with the integrated tool Synplify 7.6, and the operating frequency of 80.3 MHz can be obtained. Download with the front-end decoding module to Xilinx's Virtex-II 6000 FPGA, integrated into the H.264 video decoding verification platform, with a working frequency of 34MHz, and play an image in high-definition TV it is good.
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