The H.264 standard can produce high quality pictures in the case of a low yard ratio, mainly using adaptive loop filtering. H.264 uses a block of motion based on a tree-shaped structure. The block-based motion compensation can reduce the code rate well, but this also causing a square effect.
This H.264 has adopted an adaptive filtering algorithm that can reduce the square effect well, but also brings great calculation complexity. In H.264, the filtered data will be used as the reference frame of the next frame, and thus is also referred to as loop filtering. Studies have shown that in the H.264 decoding process, the motion compensation (MC) is 30%, and the loop filter (DF) accounts for about 20% decoded time, so a good design MC and DF have the performance of the decoder. important.
1 Data for filtering process
In H.264, the macroblock in the decoding in the case of MBAFF appears in the form of a macroblock pair. Therefore, in the storage of data, it is considered to be stored in units of data in one macroblock pair. In a macroblock pair, the data that needs to operate during the entire process is shown in Figure 1. Each of these small squares represents a 44-pixel Block, which requires the data referred to by using the UP when filtering the MB_UP macroblock. This design supports MBAFF, which requires the conversion of frames and field during filtering, so it is to be used Two lines of blocks. A column data indicated by LEFT in the figure is required when the left BLOCK is filtered.
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Figure 1 data in the filter
2 DRAM planning and design
DRAM is a low cost, large capacity, and a wide range of storage media, which is very rapid to large-scale data. However, due to the concept of row in the DRAM. In the case of different ROWs, the DRAM must turn off the current ROW and activate the required ROW, which causes a lot of Overhead. Imagine 10 data of the same ROW with 10 data being in 10 row, the latter time spent will be 5 to 6 times the former. Therefore, DRAM is not suitable for random dispersion data access.
Due to the presence of ROW, the design of the data structure in the DRAM is particularly important. To minimize access between different row, this can improve the access efficiency of the data. The DRAM of 64-bit is used in this design, and the pixel value of 8 points can be stored. A image brightness y, chroma UV is stored in a continuous space, respectively.
The final image after the H.264 decoded is stored in the DRAM, and the display module is constantly taking out the data from the DRAM to the display, and the motion compensation unit also removes the data of the reference frame from the DRAM. Therefore, the bandwidth of DRAM is particularly nervous. Rational allocation of DRAM's bandwidth is an important aspect to be considered in the design. Since many modules are required to operate the DRAM, in order to effectively manage the DRAM, the DRAMControl module is set to control the DRAM.
3 DRAMCONTROL module design
The DRAMControl module controls the interaction of DRAM and other modules outside, which is the interface of DRAM and other modules outside. The main function includes the DRAM's automatic refresh, the generation of the DRAM command, etc. Because the status of the DRAM is more, the state machine is used in this design. The state diagram is shown in Figure 2.
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Figure 2 Status Transfer Chart in DRAMCONTROL
A uniform refresh mode is used in the design, and every other time, after the "iDle → Prechall → Autorf → iDle" process is completed once. The main body of the state transition is the read and write operation process, and the decision status is determined by a clock cycle to determine whether the ROW to be executed in the current operation is in an active state. If it is not activated, it is necessary to turn off the current in the active state, and then activate the desired ROW (completes through the Prech and Act status); if activated, read / write operations are performed. For write operations, the three states of the macroblock, the left macroblock, and the own macroblock are updated after the filter is over H.264, and the three states written to the WriteUp or Writeleft and Write, and these states are implemented. The seamless connection on the time constitutes a completely coherent Burst write; if the data block of the upper macroblock or the data block of the left macroblock is in a row different from the data block of the macroblock to be filtered, in the WriteUp or Writelef status Realizing the writing of data blocks in this TILE, the write efficiency of this situation is obviously downward than in the same ROW, but this is inevitable, when the macroblock is in the leftmost or top of this ROW It is inevitably belonging to other ROW. In this design, the DRAM an address plock block and the same line of the next block, so this is the most avoided operation of the ROW. For other cases of writing, use the WRITE state to complete. Technology area
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