In 2003, new video compression standard H.264 / MPEG-4 -10AVC was introduced, referred to as H.264 / AVC. H.264 / AVC uses a range of new compression methods [1] to achieve a better compression effect, and its compression ratio is 1.5 to 2 times the conventional standard. Therefore, related research and hardware implementation based on this standard is important. The key to video compression hardware implementation is to code the code module, especially the coding module is the core. This paper mainly studies the 44 integer transformation quantitative core in the coding module, proposes the optimization method of hardware implementation, and uses the Verilog HDL language to perform hardware design and integration.
1 44 principle of integer transformation quantization core
In the previous video coding standards such as MPEG-2 and H.263, all of the predicted residual data is a basic calculation operation of the 88 discrete cosine transform (DCT) [1] as the transformation; and encoded at H.264 / AVC In the standard, an integer transformation based on 44 pixel blocks is used in a similar DCT transform. Since the size of the conversion block is reduced, the division of the moving object is more accurate, and the connection error at the edge of the moving object is greatly reduced.
For integer transform, the transformation formula of 4 × 4 pixel block [3] is:
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In the formula (CXCT), the two-dimensional transform core, the EF is the zoom factor matrix, and the symbol represents the elements of each element in the CXCT matrix and the elements of the same position in the EF matrix, A = 1/2, b =
. In order to compress the data more effectively, it is necessary to use a quantized method to damage the transformed data. At the same time, since the integer transformation needs to utilize the normalized factor of the matrix row vector for coefficient scaling processing, to reduce the amount of conversion, zoom the transformed coefficient in the H.264 / AVC standard and quantitative operation processing, avoid complex Real aspects and division operations are more conducive to hardware implementation.
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For quantitative mode, the forward quantization operation can be achieved by the following formula [3]:
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In the formula, Zij is a quantified coefficient; Wij is the element in the transformation matrix W = CXCT; MF =
· 2Q, PF is called the zoom factor, according to the different positions of the element in the array block, the value is shown in Table 1, QSTEP is quantified, from 0 to 51 to 52 quantization parameter QP decisions, QP increase 1, Qstep increased by 12.5%; Q = 15 + qp / 6, qp / 6 takes the integer; for the intra macroblock F, 2Q / 3, the inter-frame macroblock f takes 2Q / 6. It should be noted that the value of the MF can be obtained by simple calculation according to the value of PF and QP, and forms a table, and hardware operations can be achieved by checking the table, and effectively improves the calculation speed.
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2 4 × 4 integer transformation quantization core optimization design
In order to further improve the speed of hardware, reduce hardware overhead, and the following optimization method is used in the design:
(1) When obtaining the change of the changing case W = CXCT, the X column transformation (matrix left) is separated from the row transformation (matrix right), and the two-dimensional transform is divided into two one-dimensional Transform, and is implemented using a fast-shaped algorithm [4]. A fast algorithm of one-dimensional transform is implemented as shown in Figure 1, where the transformation can be expressed as follows:
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For each column transformation, it is necessary to perform 8 addition and 2 shift operations, and the row speed can be translated according to the nature ABT = (BAT) T of the matrix, and the result matrix after the column transition will be transferred first. The same conversion form operation. This makes a transform for 4 × 4-point data, and it can be done with 8 × 8 addition and 2 × 8 shift operations. Technology area
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