Abstract: This paper proposes a high-definition low code stream security camera SOC implementation based on low-cost FPGA, which has been fully implemented, and created a primary river of HD low-code stream security camera SOC.
1 Overview
At present, the core SOC of HD H.264 cameras is basically ASIC, while FPGA has developed a rapid programmable device in recent years, how can there be a place in the SOC field of HD H.264 cameras? This is the goal of our design needs to be implemented.
2. Design features
Compared with ASIC, FPGA features a strong function, flexible design, upgrade, work results can accumulate, NRE low, but chip prices are more expensive than ASIC, so we must find an application area that can reach price balance, we according to these years Smartphone and 3G network development rapidly, refer to the technical indicators of the first generation of telecom operators, directly positioning design indicators at less than 512kbps and resolutions of 1280x720x25fps, currently implementing these indicators on the market almost No, this is a good opportunity for FPGA.
The 512kbps code limit is mainly to take into account the upload capacity of ADSL and home optical transceivers, and can also utilize 3G uploading video, reduce the smartphone's code stream download pressure; 1280x720 is the mainstream resolution of smartphones, naturally need the corresponding video source If D1 or CIF is displayed, the effect is definitely not ideal.
Our goal is to do a reference design that can be used directly in production. In addition to design indicators, we have to consider prices and practical, so we chose low-cost Cyclone IV series, and also achieves all of the general webcams. Such as H.264 compression, 720P25 frames, two-way voice, important area and privacy zone definition, intelligent analysis, mobile detection, sound detection, PoE power supply, etc.
3. Implement the key to HD low-code stream H.264 camera SOC
In general, 128072025fps code streams are around 2Mbps, how to reduce the stream? In addition to using the H.264 encoder of Mail Profile with Cabac, you also need to analyze the video image, and in terms of frame rate, resolution, video quality, etc., to get the best video effect under 512 kbps code. In order to achieve such purposes, complex flexible control is required, and FPGAs can meet this needs.
4. HD low-code stream H.264 camera structure
The structure of HD low-code stream H.264 cameras is as follows:
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Figure 1 Structure diagram of HD low code stream H.264 camera
The internal structure of FPGA is shown below:
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Figure 2 Interior structure of FPGA
FPGA selection
In the structure of the HD low-code stream H.264 camera, in addition to image sensors, memory, power supplies, all functions such as image processing, H.264 encoding, protocol processing, parameter management, media stream sending, etc. are fpga Realization, FPGA is the SOC of HD low-code stream H.264 camera; there are only a few of the world's FPGA producers, and there are not many products, and use FPGA to implement HD low-code stream H.264 cameras SOC, choose A suitable FPGA is very important. The option of FPGA mainly considers three factors: speed, cost and structure; each FPGA producer has multiple FPGA series, each series of speed, performance and price are different, to make HD The cost of the low code stream H.264 camera SOC is as low as possible, the lowest cost is selected, and the FPGA we choose is the Cyclone IV series of Altera, the model is EP4CE115F23C8, and Cyclone IV is a low cost series, which is also costly In the series of FPGAs, the speed of Cyclone IV is the fastest; the structure of the FPGA is also important to image processing, especially the number of memory and multipliers, the H.264 algorithm is in units of macroblocks, and will inevitably The input and output and cache of the macroblock are involved, and the data of the 1 macro block is 384 bytes (256 bytes brightness data and 128 byte chroma data). If you take into account the input and output, you must set up, That is, 768 bytes, 1 M9K memory block with Cyclone IV, exactly, from above, can see that the FPGA for image processing is small for internal memory, such as 1kb), more memory blocks, and more, The requirements for multipliers are also quantity; when we choose FPGA, Cyclone IV is a maximum memory logic ratio and multiplier logic ratio in all low cost FPGAs, which is suitable for image processing. , Reading the full text, the technology area
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