The input and output port HT48R05A-1 single-chip provides 13 bidirectional input and output ports, and the label is PA to the PC, which corresponds to [12h], [14h], [16h], [16h], respectively, in RAM, respectively. All I / O ports can be used as input or output. In terms of input, these ports do not have latching function, that is, input data must be in "MOV A, [M]" (M = 12H, 14H, 16H) instructions. The T2 rising edge is ready, for the output, all the data is latched and remain unchanged until the output latch is rewritten. Each I / O port has its own control register (PAC, PBC, and PCC) to control the settings of the input / output. Using the control register, the CMOS output or Smitt trigger input can be dynamically changed under software. To be set to the input function, the corresponding control bit must be written "1". The input of the signal source is also dressed in the control register. If a bit of the control register is "1", the input signal is a state of reading from this pin (PAD), but if the value of a bit of the control register is "" 0, then the content of the latch will be sent to the internal bus, the latter, can happen in the Read-Modification-Write instruction instruction. For output functions, you can only be set to CMOS output. These control registers are 13h, 15h, and 17h corresponding to RAM. After the chip reset, these input / output ports will be high or floating state (depending on whether the pull-up resistance is selected), each input / output latch position can be set [M] .i or CLR [M] The instruction is set or cleared, (m = 12h, 14h, and 16h). Some instructions will first enter the data and then output operation. For example, set [m] .i, CLR [M] .i, CPL [M] and CPLA [M] instructions, read the status of the input port to the CPU, perform this operation (bit operation), then write the data back to Lock or accumulator. Each port of PA has the function of awakening the system. The high 6-bit and Pb port of the PC port is physically absent. Read these bits will return "0", and the result of writing these bits is invalid. operate. All I / O ports can have the selection of pull-up resistors. Once the pull-up resistor is selected, all I / O ports have pull-up resistors, and must be noted: no pull-up resistor I / O port work in input The mode will generate a floating phenomenon. PB0 and PB1 respectively with BZ and BZ (non) shared pins, if BZ and BZ (non) options are selected, the output signals when PB0 and PB1 in output mode will be a PFD signal generated by an overflow signal of the timing / counter. When entering mode, always maintain its original function, once BZ and BZ (non) options are selected, the buzzer's output signal is only controlled by the PB0 data register, the I / O function of PB0 and PB1 is as follows. Show:
HT48R05A-1 PB0, PB1 I / O function
PB0 I / O
I
I
I
I
O
O
O
O
O
O
PB0 I / O
I
O
O
O
I
I
I
O
O
O
PB0 / PB1 mode
X
C
B
B
C
B
B
C
B
B
PB0 data
X
X
O
1
Di
0
1
D0
O
1
PB1 data
X
Di
X
X
X
X
X
D1
X
X
PB0 PAD status
I
I
I
I
Di
0
B
D0
O
B
PB1 PAD status
1
Di
0
B
1
1
1
D1
0
B
Note: I: Input, O: Output, D, D0, D1: Data B: Buzzer Options, BZ or Bz (Non), X: Arbitrary Value C: CMOS Output PC0, PC1 is int and TMR shared pin .
In order to avoid excessive power consumption in the floating state, it is recommended to set the unused or not connected to the external I / O port to be set to the output pin. The mask options show various mask options of such a single chip microcomputer. In order to meet the functionality of the system, all mask options must be correctly defined.
HT48R05A-1 mask option
serial number
Option
1
WDT clock source, WDTOSC FTID
2
WDT Allow / Browless: Allow / Prohibition
3
LVD Allow / Browless: Allow / No
4
CLR WDT instruction: one or two clear WDT instructions
5
System oscillator: RC or quartz crystal
6
Pull resistance (PA-PC): Select a pull-up power or no pull-free resistance
Seduce
BZ option: Allow / disable
8
PA0-PA7 wake-up function: Allow / prohibition
9
Lock: Do not lock / lock, read full text, technology area
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