Hi3510 Working Principle HI3510 -H.264 BP Algorithm Video Compression Chip HI3510 is a video compression chip based on H.264 BP algorithm, which is a video compressed chip based on the H.264 BP algorithm, which uses ARM + DSP + hardware acceleration engine multi-core high integration SOC Framework, with powerful video processing functions. Real-time coding performance of DVD image quality can be adaptively adapt to various network environments, ensuring clarity and real-time, low-rate H.264 encoding technology greatly reduces network storage, and adds DES / 3DES. The decryption hardware engine ensures network security. The Hi3510 is used in a 0.13μm process, the LFBGA400 package, the size of 19 × 19mm, the pin spacing is 0.8mm, the interior integration includes digital video interface, USB, ETH, I2S, I2C, GPIO, SPI, UART, SDRAM, DDR and other interfaces To meet the development of various application scenarios, it can greatly reduce the BOM cost of the equipment. The HI3510 works: The video input unit receives the digital video information output by the VADC via the ITU-R BT.601 / 656 interface, and writes the received original image into the outer memory (SDR SDRAM or DDR SDRAM) via the AHB bus. Video codec read images from outside, perform motion estimation (inter prediction), intra prediction, DCT transformation, quantization, entropy coding (CAVLC + Exp-golomb), IDCT transformation, inversion, motion compensation, etc. Operation, it will eventually write to the outside of the naked code stream (the reference frame of the next frame) in accordance with the H.264 protocol; the video output unit reads the image from the outside and passed the ITU-R BT. The .601 / 656 interface is sent to the VDAC to display, the demand for the application is different, and the image content read from the outside is different. When the input image is required, the video output unit reads the original from the outside. Image, when you need to view the encoder of the video encoder, the video output unit reads the encoded reconstructed frame from the outside; ARM is the encapsulation of the codeward output by the video encoder, and then send the network port to achieve Video on demand service. As shown in Figure 1, the chip is composed of an ARM + DSP + video encoding accelerator + graphics engine scaler integrated peripheral interface, and internal integration includes digital watermarks, DES / 3DES algorithms, making single-chip adaptation All work, reduce development difficulty with other chips, and exempt manufacturers repeatedly develop the contents of the standard part of the algorithm, which greatly reduces the entry threshold for equipment manufacturers. With the development kits of Haisi's different application forms, various products such as PMP, Visual Phone, Network Monitoring, PVR, Visual Intercom are available. Figure 1: Hi3510 H.264 audio video codec SOC logic block diagram. The implementation of the HI3510 codec scheme is a codec chip of the SOC architecture, and the HI3510 is fully considered to compatibility and the convenience of use when designing. Support for almost all companies produced series of AD / DA chips. The HI3510 can be operated as a separate encoder or as an independent decoder, or simultaneously codec work, fully considering the various applications of the codec market. The HI3510 is a typical multi-applied single-chip solution that greatly reduces the BOM composition and cost of the device. As shown in FIG. 2, the chip is used as a result of simultaneous decoding. Figure 2: Hi3510 is a typical multi-applied single-chip solution. I3510 Code Application Hi3510 comes with a Linux operating system (simultaneous open operating system) and ARM processor, allowing the chip to achieve many rich application capabilities in addition to codec function. As shown in Figure 2, the digital, compression, and storage of the composite video signal can be realized as long as an ordinary AD is attached. The HI3510 development package provides a top-level API interface, you can call all chip functions and develop your own personalization. Figure 3 is an application design of the encoding scheme of the chip. Figure 3: Application design of Hi3510 chip coding scheme. The decoder application is the same as the encoder in the architecture (convenient plan can be consistent, you can implement a hardware to meet the needs, just need software upgrade). The decoder only needs to match the DA chip (if the LCD number screen can save this chip), you can achieve the effect of decoding the data stream stream, and implements the menu operation of the user's human machine interaction through the GUI or OSD, implementing a similar function such as PMP. Applications. Figure 4 is an application design of a decoding scheme for a chip. Figure 4: Application design of the Hi3510 chip decoding scheme. This paper provides technical support for the application of the H.264 standard, providing a video of network transmission, especially if low bandwidth (such as wireless transmission mode). Today, in today's market, the market requires designers to launch the product faster, and in order to maintain the competitiveness of the product, maintain enough advantages in product prices, product application features, especially in the field of multimedia markets. Haisi's SOC chip is based on the standard algorithm, giving the designer's largest flexibility to design the right product, which greatly reduces the investment cost of the manufacturer and shortens the time of the manufacturer's introduction, and prepares for the market. . Technology area
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